Remove RealWireDataSource::OutPort

pc2 · Jul 9, 2024 · 35a1a8c · 35a1a8c
1 parent 2136557
commit 35a1a8c
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Showing 5 changed files with 2 additions and 6 deletions.
diff --git a/src/codegen_fallback.rs b/src/codegen_fallback.rs
@@ -170,7 +170,7 @@ impl<'g, 'out, Stream : std::fmt::Write> CodeGenerationContext<'g, 'out, Stream>
                 RealWireDataSource::Constant { value } => {
                     writeln!(self.program_text, " = {};", value.to_string())?;
                 }
-                RealWireDataSource::ReadOnly | RealWireDataSource::OutPort { sub_module_id:_, port_id:_ } => {
+                RealWireDataSource::ReadOnly => {
                     writeln!(self.program_text, ";")?;
                 }
                 RealWireDataSource::Multiplexer{is_state, sources : _} => {
@@ -231,7 +231,6 @@ impl<'g, 'out, Stream : std::fmt::Write> CodeGenerationContext<'g, 'out, Stream>
                     writeln!(self.program_text, "end")?;
                 }
                 RealWireDataSource::ReadOnly => {}
-                RealWireDataSource::OutPort { sub_module_id:_, port_id:_ } => {}
                 RealWireDataSource::Select{root : _, path : _} => {}
                 RealWireDataSource::UnaryOp{op : _, right : _} => {}
                 RealWireDataSource::BinaryOp{op : _, left : _, right : _} => {}

diff --git a/src/instantiation/execute.rs b/src/instantiation/execute.rs
@@ -306,7 +306,7 @@ impl<'fl, 'l> InstantiationContext<'fl, 'l> {
             let source = if port_data.is_input {
                 RealWireDataSource::Multiplexer { is_state: None, sources: Vec::new() }
             } else {
-                RealWireDataSource::OutPort { sub_module_id, port_id }
+                RealWireDataSource::ReadOnly
             };
             let domain = submodule_instruction.local_interface_domains[port_data.domain];
             let new_wire = self.wires.alloc(RealWire {

diff --git a/src/instantiation/latency_count.rs b/src/instantiation/latency_count.rs
@@ -73,7 +73,6 @@ impl RealWireDataSource {
     fn iter_sources_with_min_latency<F : FnMut(WireID, i64)>(&self, mut f : F) {
         match self {
             RealWireDataSource::ReadOnly => {}
-            RealWireDataSource::OutPort { .. } => {}
             RealWireDataSource::Multiplexer { is_state: _, sources } => {
                 for s in sources {
                     f(s.from.from, s.from.num_regs);

diff --git a/src/instantiation/mod.rs b/src/instantiation/mod.rs
@@ -59,7 +59,6 @@ pub struct MultiplexerSource {
 #[derive(Debug)]
 pub enum RealWireDataSource {
     ReadOnly,
-    OutPort{sub_module_id : SubModuleID, port_id : PortID},
     Multiplexer{is_state : Option<Value>, sources : Vec<MultiplexerSource>},
     UnaryOp{op : UnaryOperator, right : WireID},
     BinaryOp{op : BinaryOperator, left : WireID, right : WireID},

diff --git a/src/instantiation/typecheck.rs b/src/instantiation/typecheck.rs
@@ -23,7 +23,6 @@ impl<'fl, 'l> InstantiationContext<'fl, 'l> {
 
             match &this_wire.source {
                 RealWireDataSource::ReadOnly => {}
-                RealWireDataSource::OutPort { sub_module_id:_, port_id:_ } => {} // Currently all ports have their types assigned at execution time
                 RealWireDataSource::Multiplexer { is_state:_, sources:_ } => {} // Do muxes later. 
                 &RealWireDataSource::UnaryOp { op, right } => {
                     let right_typ = self.wires[right].typ.clone();