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Compacted generated verilog
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@VonTum
VonTum committed Dec 18, 2023
1 parent 660b9c0 commit bca3d75
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Showing 2 changed files with 32 additions and 23 deletions.
45 changes: 27 additions & 18 deletions src/codegen_fallback.rs
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
use std::{iter::zip, ops::Deref};

use crate::{ast::{Module, Value, IdentifierType}, instantiation::{InstantiatedModule, RealWireDataSource, StateInitialValue, ConnectToPathElem}, linker::{Linker, NamedUUID, get_builtin_uuid}, arena_alloc::UUID, typing::ConcreteType, tokenizer::get_token_type_name, flattening::WireSource};
use crate::{ast::{Module, Value, IdentifierType}, instantiation::{InstantiatedModule, RealWireDataSource, StateInitialValue, ConnectToPathElem}, linker::{NamedUUID, get_builtin_uuid}, arena_alloc::UUID, typing::ConcreteType, tokenizer::get_token_type_name, flattening::WireSource};

fn get_type_name_size(id : NamedUUID) -> u64 {
if id == get_builtin_uuid("int") {
Expand Down Expand Up @@ -55,15 +55,15 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
}
program_text.push_str(");\n");

for (id, w) in &instance.wires {
for (_id, w) in &instance.wires {
if let WireSource::NamedWire{read_only : _, identifier_type, decl_id : _} = &md.flattened.instantiations[w.original_wire].extract_wire().inst {
// Don't print named inputs and outputs, already did that in interface
match identifier_type {
IdentifierType::Input | IdentifierType::Output => {continue;}
IdentifierType::Local | IdentifierType::State => {}
}
}
let wire_or_reg = if let RealWireDataSource::Multiplexer{is_state: initial_value, sources} = &w.source {
let wire_or_reg = if let RealWireDataSource::Multiplexer{is_state: initial_value, sources: _} = &w.source {
if let StateInitialValue::NotState = initial_value {
"/*mux_wire*/ reg"
} else {
Expand All @@ -75,10 +75,27 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
program_text.push_str(&typ_to_verilog_array(&w.typ));
program_text.push(' ');
program_text.push_str(&w.name);

match &w.source {
RealWireDataSource::UnaryOp { op, right } => {
program_text.push_str(&format!(" = {}{}", get_token_type_name(op.op_typ), instance.wires[*right].name));
}
RealWireDataSource::BinaryOp { op, left, right } => {
program_text.push_str(&format!(" = {} {} {}", instance.wires[*left].name, get_token_type_name(op.op_typ), instance.wires[*right].name));
}
RealWireDataSource::ArrayAccess { arr, arr_idx } => {
program_text.push_str(&format!(" = {}[{}]", instance.wires[*arr].name, instance.wires[*arr_idx].name));
}
RealWireDataSource::Constant { value } => {
program_text.push_str(&format!(" = {}", value_to_str(value)));
}
RealWireDataSource::ReadOnly => {}
RealWireDataSource::Multiplexer{is_state : _, sources : _} => {}
}
program_text.push_str(";\n");
}

for (id, sm) in &instance.submodules {
for (_id, sm) in &instance.submodules {
program_text.push_str(&sm.instance.name);
program_text.push(' ');
program_text.push_str(&sm.name);
Expand All @@ -93,7 +110,7 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
program_text.push_str("\n);\n");
}

for (id, w) in &instance.wires {
for (_id, w) in &instance.wires {
match &w.source {
RealWireDataSource::ReadOnly => {}
RealWireDataSource::Multiplexer { is_state, sources } => {
Expand All @@ -102,7 +119,7 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
StateInitialValue::NotState => {
program_text.push_str(&format!("/*always_comb*/ always @(*) begin\n\t{output_name} <= 1'bX; // Not defined when not valid\n"));
}
StateInitialValue::State { initial_value } => {
StateInitialValue::State{initial_value : _} => {
program_text.push_str(&format!("/*always_ff*/ always @(posedge clk) begin\n"));
}
}
Expand All @@ -127,18 +144,10 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
}
program_text.push_str("end\n");
}
RealWireDataSource::UnaryOp { op, right } => {
program_text.push_str(&format!("assign {} = {}{};\n", w.name, get_token_type_name(op.op_typ), instance.wires[*right].name));
}
RealWireDataSource::BinaryOp { op, left, right } => {
program_text.push_str(&format!("assign {} = {} {} {};\n", w.name, instance.wires[*left].name, get_token_type_name(op.op_typ), instance.wires[*right].name));
}
RealWireDataSource::ArrayAccess { arr, arr_idx } => {
program_text.push_str(&format!("assign {} = {}[{}];\n", w.name, instance.wires[*arr].name, instance.wires[*arr_idx].name));
}
RealWireDataSource::Constant { value } => {
program_text.push_str(&format!("assign {} = {};\n", w.name, value_to_str(value)));
}
RealWireDataSource::UnaryOp{op : _, right : _} => {}
RealWireDataSource::BinaryOp{op : _, left : _, right : _} => {}
RealWireDataSource::ArrayAccess{arr : _, arr_idx : _} => {}
RealWireDataSource::Constant{value : _} => {}
}
}

Expand Down
10 changes: 5 additions & 5 deletions src/flattening.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ use std::{ops::{Deref, Range}, iter::zip};
use crate::{
ast::{Span, Value, Module, Expression, SpanExpression, LocalOrGlobal, Operator, AssignableExpression, SpanAssignableExpression, Statement, CodeBlock, IdentifierType, GlobalReference, TypeExpression, DeclIDMarker, DeclID},
linker::{Linker, Named, Linkable, get_builtin_uuid, FileUUID, NamedUUID},
errors::{ErrorCollector, error_info}, arena_alloc::{ListAllocator, UUID, UUIDMarker, FlatAlloc}, tokenizer::kw, typing::{Type, typecheck_unary_operator, get_binary_operator_types, typecheck, typecheck_is_array_indexer}, block_vector::BlockVec
errors::{ErrorCollector, error_info}, arena_alloc::{ListAllocator, UUID, UUIDMarker, FlatAlloc}, tokenizer::kw, typing::{Type, typecheck_unary_operator, get_binary_operator_types, typecheck, typecheck_is_array_indexer}
};

#[derive(Debug,Clone,Copy,PartialEq,Eq,Hash)]
Expand Down Expand Up @@ -158,7 +158,7 @@ impl<'l, 'm, 'fl> FlatteningContext<'l, 'm, 'fl> {
}
};
let func_instantiation = &self.instantiations[func_instantiation_id];
let Instantiation::SubModule{module_uuid, name, typ_span, interface_wires} = func_instantiation else {unreachable!("It should be proven {func_instantiation:?} was a Module!");};
let Instantiation::SubModule{module_uuid, name : _, typ_span : _, interface_wires} = func_instantiation else {unreachable!("It should be proven {func_instantiation:?} was a Module!");};
let Named::Module(md) = &self.linker.links.globals[*module_uuid] else {unreachable!("UUID Should be a module!");};
let (inputs, output_range) = md.interface.get_function_sugar_inputs_outputs();

Expand Down Expand Up @@ -223,7 +223,7 @@ impl<'l, 'm, 'fl> FlatteningContext<'l, 'm, 'fl> {
self.instantiations.alloc(Instantiation::Wire(WireInstance{typ : output_type, inst : WireSource::BinaryOp{op : *op, left, right}}))
}
Expression::Array(arr_box) => {
let (left, right, bracket_span) = arr_box.deref();
let (left, right, _bracket_span) = arr_box.deref();
let arr = self.flatten_single_expr(left, condition)?;
let arr_idx = self.flatten_single_expr(right, condition)?;

Expand Down Expand Up @@ -251,7 +251,7 @@ impl<'l, 'm, 'fl> FlatteningContext<'l, 'm, 'fl> {
Some(match expr {
AssignableExpression::Named{local_idx} => {
let root = self.decl_to_flat_map[*local_idx];
let WireSource::NamedWire { read_only, identifier_type : _, decl_id } = &self.instantiations[root].extract_wire().inst else {
let WireSource::NamedWire { read_only, identifier_type : _, decl_id : _ } = &self.instantiations[root].extract_wire().inst else {
unreachable!("Attempting to assign to a Instantiation::PlainWire")
};
if *read_only {
Expand All @@ -262,7 +262,7 @@ impl<'l, 'm, 'fl> FlatteningContext<'l, 'm, 'fl> {
ConnectionWrite{root, path : Vec::new(), span : *span}
}
AssignableExpression::ArrayIndex(arr_box) => {
let (arr, idx, bracket_span) = arr_box.deref();
let (arr, idx, _bracket_span) = arr_box.deref();
let flattened_arr_expr_opt = self.flatten_assignable_expr(arr, condition);

let idx_local = self.flatten_single_expr(idx, condition)?;
Expand Down

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