Refactor test logic to share common check/update logic

tests/gold/test_when_alwcomb_order_complex.v

@@ -1,5 +1,5 @@
 // Generated by CIRCT firtool-1.48.0-34-g7018fb13b
-module test_when_alwcomb_order(
+module test_when_alwcomb_order_complex(
   input  [7:0] I,
   input  [1:0] S,
   output [7:0] O

tests/gold/test_when_alwcomb_order_nested.v

@@ -1,5 +1,5 @@
 // Generated by CIRCT firtool-1.48.0-34-g7018fb13b
-module test_when_alwcomb_order(
+module test_when_alwcomb_order_nested(
   input  struct packed {logic x; logic [7:0] y; } I,
   input                                           S,
   output struct packed {logic x; logic [7:0] y; } O

tests/gold/test_when_alwcomb_order_nested_2.v

@@ -1,5 +1,5 @@
 // Generated by CIRCT firtool-1.48.0-34-g7018fb13b
-module test_when_alwcomb_order(
+module test_when_alwcomb_order_nested_2(
   input  struct packed {logic x; logic [7:0] y; }[2:0] I,
   input                                                S,
   output struct packed {logic x; logic [7:0] y; }      O

tests/test_when.py

@@ -1803,6 +1803,22 @@ class test_when_emit_asserts_tuple_elab(m.Circuit):
     assert check_gold(__file__, "test_when_emit_asserts_tuple_elab.mlir")
 
 
+def _check_or_update(circ):
+    # We check verilog here because the alwcomb order was "legal" MLIR.
+    m.compile(f"build/{circ.name}", circ, output="mlir-verilog")
+
+    _file = f"{circ.name}.v"
+    if check_gold(__file__, _file):
+        return
+    verilator_path = os.path.join(
+        os.path.dirname(__file__),
+        "build",
+        _file
+    )
+    assert not os.system(f"verilator --lint-only {verilator_path}")
+    update_gold(__file__, _file)
+
+
 def test_when_alwcomb_order():
     class test_when_alwcomb_order(m.Circuit):
         io = m.IO(I=m.In(m.Bits[8]), S=m.In(m.Bits[1]), O=m.Out(m.Bits[8]))
@@ -1815,26 +1831,11 @@ class test_when_alwcomb_order(m.Circuit):
             x @= ~io.I
             io.O @= ~x
 
-    m.compile(
-        "build/test_when_alwcomb_order",
-        test_when_alwcomb_order,
-        output="mlir-verilog"
-    )
-
-    # We check verilog here because the alwcomb order was "legal" MLIR.
-    if check_gold(__file__, "test_when_alwcomb_order.v"):
-        return
-    verilator_path = os.path.join(
-        os.path.dirname(__file__),
-        "build",
-        "test_when_alwcomb_order.v"
-    )
-    assert not os.system(f"verilator --lint-only {verilator_path}")
-    update_gold(__file__, "test_when_alwcomb_order.v")
+    _check_or_update(test_when_alwcomb_order)
 
 
 def test_when_alwcomb_order_complex():
-    class test_when_alwcomb_order(m.Circuit):
+    class test_when_alwcomb_order_complex(m.Circuit):
         io = m.IO(I=m.In(m.Bits[8]), S=m.In(m.Bits[2]), O=m.Out(m.Bits[8]))
         x = m.Bits[8]()
 
@@ -1850,30 +1851,15 @@ class test_when_alwcomb_order(m.Circuit):
             io.O @= ~x
             x @= ~io.I
 
-    m.compile(
-        "build/test_when_alwcomb_order_complex",
-        test_when_alwcomb_order,
-        output="mlir-verilog"
-    )
-
-    # We check verilog here because the alwcomb order was "legal" MLIR.
-    if check_gold(__file__, "test_when_alwcomb_order_complex.v"):
-        return
-    verilator_path = os.path.join(
-        os.path.dirname(__file__),
-        "build",
-        "test_when_alwcomb_order_complex.v"
-    )
-    assert not os.system(f"verilator --lint-only {verilator_path}")
-    update_gold(__file__, "test_when_alwcomb_order_complex.v")
+    _check_or_update(test_when_alwcomb_order_complex)
 
 
 def test_when_alwcomb_order_nested():
     class T(m.Product):
         x = m.Bit
         y = m.Bits[8]
 
-    class test_when_alwcomb_order(m.Circuit):
+    class test_when_alwcomb_order_nested(m.Circuit):
         io = m.IO(I=m.In(T), S=m.In(m.Bit), O=m.Out(T))
         x = T()
 
@@ -1886,30 +1872,15 @@ class test_when_alwcomb_order(m.Circuit):
             x.x @= ~io.I.x
             x.y @= ~io.I.y
 
-    m.compile(
-        "build/test_when_alwcomb_order_nested",
-        test_when_alwcomb_order,
-        output="mlir-verilog"
-    )
-
-    # We check verilog here because the alwcomb order was "legal" MLIR.
-    if check_gold(__file__, "test_when_alwcomb_order_nested.v"):
-        return
-    verilator_path = os.path.join(
-        os.path.dirname(__file__),
-        "build",
-        "test_when_alwcomb_order_nested.v"
-    )
-    assert not os.system(f"verilator --lint-only {verilator_path}")
-    update_gold(__file__, "test_when_alwcomb_order_nested.v")
+    _check_or_update(test_when_alwcomb_order_nested)
 
 
 def test_when_alwcomb_order_nested_2():
     class T(m.Product):
         x = m.Bit
         y = m.Bits[8]
 
-    class test_when_alwcomb_order(m.Circuit):
+    class test_when_alwcomb_order_nested_2(m.Circuit):
         io = m.IO(I=m.In(m.Array[3, T]), S=m.In(m.Bit), O=m.Out(T))
         x = T()
 
@@ -1921,22 +1892,7 @@ class test_when_alwcomb_order(m.Circuit):
             io.O.y @= x.y
             x @= io.I[2]
 
-    m.compile(
-        "build/test_when_alwcomb_order_nested_2",
-        test_when_alwcomb_order,
-        output="mlir-verilog"
-    )
-
-    # We check verilog here because the alwcomb order was "legal" MLIR.
-    if check_gold(__file__, "test_when_alwcomb_order_nested_2.v"):
-        return
-    verilator_path = os.path.join(
-        os.path.dirname(__file__),
-        "build",
-        "test_when_alwcomb_order_nested_2.v"
-    )
-    assert not os.system(f"verilator --lint-only {verilator_path}")
-    update_gold(__file__, "test_when_alwcomb_order_nested_2.v")
+    _check_or_update(test_when_alwcomb_order_nested_2)
 
 
 # TODO: In this case, we'll generate elaborated assignments, but it should