Merge branch 'master' into coreir-optional

phanrahan · Sep 21, 2023 · 23db17a · 23db17a
2 parents 19f6133 + 4387b64
commit 23db17a
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diff --git a/magma/primitives/when.py b/magma/primitives/when.py
@@ -316,7 +316,6 @@ def get_when_assert_wire(self, port):
             temp = Wire(type(port).undirected_t, flatten=False)(name=name)
             for value in port.driving():
                 _rewire_driven_value_or_values(value, temp.O)
-            assert not port.driving()
             temp.I @= port
             self._when_assert_wires[port] = temp.O
         return self._when_assert_wires[port]

diff --git a/magma/tuple.py b/magma/tuple.py
@@ -320,7 +320,7 @@ def wire(self, o, debug_info):
             )
             return
 
-        if self.keys() != o.keys():
+        if list(self.keys()) != list(o.keys()):
             _logger.error(
                 WiringLog(f"Cannot wire {{}} (type={type(o)}, "
                           f"keys={list(self.keys())}) to "

diff --git a/setup.py b/setup.py
@@ -44,7 +44,7 @@
         "staticfg",
         "networkx",
         "uinspect",
-        "circt==1.48.1.dev34",
+        "circt==1.51.1.dev75",
     ],
     python_requires='>=3.6',
     long_description=long_description,

diff --git a/tests/test_backend/test_mlir/golds/aggregate_constant.v b/tests/test_backend/test_mlir/golds/aggregate_constant.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module aggregate_constant(
   output struct packed {logic [7:0] x; logic [3:0] y; } y
 );

diff --git a/tests/test_backend/test_mlir/golds/aggregate_mux_wrapper.v b/tests/test_backend/test_mlir/golds/aggregate_mux_wrapper.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module aggregate_mux_wrapper(
   input  struct packed {logic [7:0] x; logic y; } a,
   input                                           s,

diff --git a/tests/test_backend/test_mlir/golds/aggregate_mux_wrapper_extend_non_power_of_two_muxes.v b/tests/test_backend/test_mlir/golds/aggregate_mux_wrapper_extend_non_power_of_two_muxes.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module aggregate_mux_wrapper(
   input  struct packed {logic [7:0] x; logic y; } a,
   input                                           s,

diff --git a/.../test_mlir/golds/aggregate_mux_wrapper_extend_non_power_of_two_muxes_flatten_all_tuples.v b/.../test_mlir/golds/aggregate_mux_wrapper_extend_non_power_of_two_muxes_flatten_all_tuples.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module aggregate_mux_wrapper(
   input  [7:0] a_x,
   input        a_y,

diff --git a/tests/test_backend/test_mlir/golds/aggregate_mux_wrapper_flatten_all_tuples.v b/tests/test_backend/test_mlir/golds/aggregate_mux_wrapper_flatten_all_tuples.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module aggregate_mux_wrapper(
   input  [7:0] a_x,
   input        a_y,

diff --git a/tests/test_backend/test_mlir/golds/complex_aggregates_nested_array.v b/tests/test_backend/test_mlir/golds/complex_aggregates_nested_array.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_aggregates_nested_array(
   input  [1:0][2:0][3:0] a,
   output [1:0][2:0][3:0] y

diff --git a/tests/test_backend/test_mlir/golds/complex_bind.v b/tests/test_backend/test_mlir/golds/complex_bind.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_bind_asserts(
   input struct packed {logic I; } I,
   input                           O,
@@ -26,7 +26,7 @@ endmodule
 
 // ----- 8< ----- FILE "bindfile.sv" ----- 8< -----
 
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 bind complex_bind complex_bind_asserts complex_bind_asserts_inst (
   .I   (I),
   .O   (Register_inst0),

diff --git a/tests/test_backend/test_mlir/golds/complex_bind_flatten_all_tuples.v b/tests/test_backend/test_mlir/golds/complex_bind_flatten_all_tuples.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_bind_asserts(
   input I_I,
         O,
@@ -26,7 +26,7 @@ endmodule
 
 // ----- 8< ----- FILE "bindfile.sv" ----- 8< -----
 
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 bind complex_bind complex_bind_asserts complex_bind_asserts_inst (
   .I_I (I_I),
   .O   (Register_inst0),

diff --git a/tests/test_backend/test_mlir/golds/complex_inline_verilog.v b/tests/test_backend/test_mlir/golds/complex_inline_verilog.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_inline_verilog(
   input  [11:0] I,
   input         CLK,

diff --git a/tests/test_backend/test_mlir/golds/complex_inline_verilog2.v b/tests/test_backend/test_mlir/golds/complex_inline_verilog2.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_inline_verilog2(
   input  [11:0] I,
   input         CLK,

diff --git a/tests/test_backend/test_mlir/golds/complex_lut.v b/tests/test_backend/test_mlir/golds/complex_lut.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module LUT(
   input  [1:0]                                         I,
   output struct packed {logic [7:0] x; logic y; }[1:0] O

diff --git a/tests/test_backend/test_mlir/golds/complex_magma_protocol.v b/tests/test_backend/test_mlir/golds/complex_magma_protocol.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_magma_protocol(
   input  [7:0] I,
   output [7:0] O

diff --git a/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports.v b/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_mixed_direction_ports(
   input  [7:0] a_0_x,
                a_1_x,

diff --git a/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.v b/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_mixed_direction_ports(
   input  [7:0] a_x,
   output [7:0] a_y

diff --git a/tests/test_backend/test_mlir/golds/complex_register_wrapper.v b/tests/test_backend/test_mlir/golds/complex_register_wrapper.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_register_wrapper(
   input  struct packed {logic [7:0] x; logic y; }                                          a,
   input  [5:0][15:0]                                                                       b,

diff --git a/tests/test_backend/test_mlir/golds/complex_register_wrapper_disable_initial_blocks.v b/tests/test_backend/test_mlir/golds/complex_register_wrapper_disable_initial_blocks.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_register_wrapper(
   input  struct packed {logic [7:0] x; logic y; }                                          a,
   input  [5:0][15:0]                                                                       b,

diff --git a/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.v b/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module Register(
   input  struct packed {logic [7:0] x; logic y; } I,
   input                                           CE,

diff --git a/tests/test_backend/test_mlir/golds/complex_register_wrapper_flatten_all_tuples.v b/tests/test_backend/test_mlir/golds/complex_register_wrapper_flatten_all_tuples.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_register_wrapper(
   input  [7:0]       a_x,
   input              a_y,

diff --git a/tests/test_backend/test_mlir/golds/complex_undriven.v b/tests/test_backend/test_mlir/golds/complex_undriven.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_undriven(
   output struct packed {logic [7:0] x; logic y; } O
 );

diff --git a/tests/test_backend/test_mlir/golds/complex_wire.v b/tests/test_backend/test_mlir/golds/complex_wire.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module complex_wire(
   input  [7:0]      I0,
   input             I1,

diff --git a/tests/test_backend/test_mlir/golds/counter.v b/tests/test_backend/test_mlir/golds/counter.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module counter(
   input         CLK,
   output [15:0] y

diff --git a/tests/test_backend/test_mlir/golds/feedthrough.v b/tests/test_backend/test_mlir/golds/feedthrough.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module feedthrough(
   input  I,
   output O

diff --git a/tests/test_backend/test_mlir/golds/multiport_memory.v b/tests/test_backend/test_mlir/golds/multiport_memory.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module multiport_memory(
   input  [1:0] raddr_0,
                raddr_1,

diff --git a/tests/test_backend/test_mlir/golds/multiport_memory_re.v b/tests/test_backend/test_mlir/golds/multiport_memory_re.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module multiport_memory_re(
   input  [1:0] raddr_0,
                raddr_1,

diff --git a/tests/test_backend/test_mlir/golds/no_outputs.v b/tests/test_backend/test_mlir/golds/no_outputs.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module no_outputs(
   input I
 );

diff --git a/tests/test_backend/test_mlir/golds/non_power_of_two_mux_wrapper.v b/tests/test_backend/test_mlir/golds/non_power_of_two_mux_wrapper.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module non_power_of_two_mux_wrapper(
   input  struct packed {logic [7:0] x; logic y; } a,
   input  [3:0]                                    s,

diff --git a/...test_backend/test_mlir/golds/non_power_of_two_mux_wrapper_extend_non_power_of_two_muxes.v b/...test_backend/test_mlir/golds/non_power_of_two_mux_wrapper_extend_non_power_of_two_muxes.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module non_power_of_two_mux_wrapper(
   input  struct packed {logic [7:0] x; logic y; } a,
   input  [3:0]                                    s,

diff --git a/...lir/golds/non_power_of_two_mux_wrapper_extend_non_power_of_two_muxes_flatten_all_tuples.v b/...lir/golds/non_power_of_two_mux_wrapper_extend_non_power_of_two_muxes_flatten_all_tuples.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module non_power_of_two_mux_wrapper(
   input  [7:0] a_x,
   input        a_y,

diff --git a/tests/test_backend/test_mlir/golds/register_array_of_bit.v b/tests/test_backend/test_mlir/golds/register_array_of_bit.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module register_array_of_bit(
   input  [3:0] I,
   input        CLK,

diff --git a/tests/test_backend/test_mlir/golds/simple_aggregates_anon_product.v b/tests/test_backend/test_mlir/golds/simple_aggregates_anon_product.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_aggregates_anon_product(
   input  struct packed {logic [7:0] x; logic [7:0] y; } a,
   output struct packed {logic [7:0] x; logic [7:0] y; } y

diff --git a/tests/test_backend/test_mlir/golds/simple_aggregates_anon_product_flatten_all_tuples.v b/tests/test_backend/test_mlir/golds/simple_aggregates_anon_product_flatten_all_tuples.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_aggregates_anon_product(
   input  [7:0] a_x,
                a_y,

diff --git a/tests/test_backend/test_mlir/golds/simple_aggregates_array.v b/tests/test_backend/test_mlir/golds/simple_aggregates_array.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_aggregates_array(
   input  [7:0][15:0] a,
   output [7:0][15:0] y,

diff --git a/tests/test_backend/test_mlir/golds/simple_aggregates_bits.v b/tests/test_backend/test_mlir/golds/simple_aggregates_bits.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_aggregates_bits(
   input  [15:0] a,
   output [15:0] y,

diff --git a/tests/test_backend/test_mlir/golds/simple_aggregates_nested_array.v b/tests/test_backend/test_mlir/golds/simple_aggregates_nested_array.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_aggregates_nested_array(
   input  [7:0][3:0][15:0] a,
   output [7:0][3:0][15:0] y

diff --git a/tests/test_backend/test_mlir/golds/simple_aggregates_product.v b/tests/test_backend/test_mlir/golds/simple_aggregates_product.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_aggregates_product(
   input  struct packed {logic [7:0] x; logic [7:0] y; } a,
   output struct packed {logic [7:0] x; logic [7:0] y; } y

diff --git a/tests/test_backend/test_mlir/golds/simple_aggregates_product_flatten_all_tuples.v b/tests/test_backend/test_mlir/golds/simple_aggregates_product_flatten_all_tuples.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_aggregates_product(
   input  [7:0] a_x,
                a_y,

diff --git a/tests/test_backend/test_mlir/golds/simple_aggregates_tuple.v b/tests/test_backend/test_mlir/golds/simple_aggregates_tuple.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_aggregates_tuple(
   input  struct packed {logic [7:0] _0; logic [7:0] _1; } a,
   output struct packed {logic [7:0] _0; logic [7:0] _1; } y

diff --git a/tests/test_backend/test_mlir/golds/simple_array_of_bit.v b/tests/test_backend/test_mlir/golds/simple_array_of_bit.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_array_of_bit(
   input  [7:0] I,
   output [7:0] O

diff --git a/tests/test_backend/test_mlir/golds/simple_array_slice.v b/tests/test_backend/test_mlir/golds/simple_array_slice.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_array_slice(
   input  [11:0][7:0] a,
   output [3:0][7:0]  y

diff --git a/tests/test_backend/test_mlir/golds/simple_bind.v b/tests/test_backend/test_mlir/golds/simple_bind.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_bind_asserts(
   input I,
         O,
@@ -25,7 +25,7 @@ endmodule
 
 // ----- 8< ----- FILE "bindfile.sv" ----- 8< -----
 
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 bind simple_bind simple_bind_asserts simple_bind_asserts_inst (
   .I   (I),
   .O   (Register_inst0),

diff --git a/tests/test_backend/test_mlir/golds/simple_clock_cast.v b/tests/test_backend/test_mlir/golds/simple_clock_cast.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_clock_cast(
   input  I,
   output O

diff --git a/tests/test_backend/test_mlir/golds/simple_comb.v b/tests/test_backend/test_mlir/golds/simple_comb.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_comb(
   input  [15:0] a,
                 b,

diff --git a/tests/test_backend/test_mlir/golds/simple_comb_verilog_prefix.v b/tests/test_backend/test_mlir/golds/simple_comb_verilog_prefix.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module proj_simple_comb(
   input  [15:0] a,
                 b,

diff --git a/tests/test_backend/test_mlir/golds/simple_compile_guard.v b/tests/test_backend/test_mlir/golds/simple_compile_guard.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module COND1_compile_guard(
   input port_0,
         port_1

diff --git a/tests/test_backend/test_mlir/golds/simple_constant.v b/tests/test_backend/test_mlir/golds/simple_constant.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_constant(
   input  [7:0] I,
   output [7:0] O

diff --git a/.../test_backend/test_mlir/golds/simple_coreir_common_lib_mux_n_wrapper_flatten_all_tuples.v b/.../test_backend/test_mlir/golds/simple_coreir_common_lib_mux_n_wrapper_flatten_all_tuples.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_coreir_common_lib_mux_n_wrapper(
   input  [7:0][5:0] I_data,
   input  [2:0]      I_sel,

diff --git a/tests/test_backend/test_mlir/golds/simple_custom_verilog_name.v b/tests/test_backend/test_mlir/golds/simple_custom_verilog_name.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_custom_verilog_name_custom_name(
   input  I,
   output O

diff --git a/tests/test_backend/test_mlir/golds/simple_decl_external.v b/tests/test_backend/test_mlir/golds/simple_decl_external.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 // external module simple_decl
 
 module simple_decl_external(

diff --git a/tests/test_backend/test_mlir/golds/simple_disallow_local_variables.v b/tests/test_backend/test_mlir/golds/simple_disallow_local_variables.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_disallow_local_variables(
   input  [1:0] x,
   input        s,

diff --git a/...s/test_backend/test_mlir/golds/simple_disallow_local_variables_disallow_local_variables.v b/...s/test_backend/test_mlir/golds/simple_disallow_local_variables_disallow_local_variables.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_disallow_local_variables(
   input  [1:0] x,
   input        s,

diff --git a/tests/test_backend/test_mlir/golds/simple_div.v b/tests/test_backend/test_mlir/golds/simple_div.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_div(
   input  [15:0] a,
                 b,

diff --git a/tests/test_backend/test_mlir/golds/simple_duplicate_symbols_disallow_duplicate_symbols.v b/tests/test_backend/test_mlir/golds/simple_duplicate_symbols_disallow_duplicate_symbols.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_duplicate_symbols(
   input        I,
   output [1:0] O

diff --git a/tests/test_backend/test_mlir/golds/simple_hierarchy.v b/tests/test_backend/test_mlir/golds/simple_hierarchy.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_comb(
   input  [15:0] a,
                 b,

diff --git a/tests/test_backend/test_mlir/golds/simple_inline_verilog.v b/tests/test_backend/test_mlir/golds/simple_inline_verilog.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_inline_verilog(
   input  I,
   output O

diff --git a/tests/test_backend/test_mlir/golds/simple_inline_verilog2.v b/tests/test_backend/test_mlir/golds/simple_inline_verilog2.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_inline_verilog2(
   input  I,
   output O

diff --git a/tests/test_backend/test_mlir/golds/simple_length_one_array.v b/tests/test_backend/test_mlir/golds/simple_length_one_array.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_length_one_array(
   input  [0:0][7:0] I,
   output [7:0]      O

diff --git a/tests/test_backend/test_mlir/golds/simple_length_one_bits.v b/tests/test_backend/test_mlir/golds/simple_length_one_bits.v
@@ -1,4 +1,4 @@
-// Generated by CIRCT firtool-1.48.0-34-g7018fb13b
+// Generated by CIRCT firtool-1.51.0-75-gbecb4c0ef
 module simple_length_one_bits(
   input  I,
   output O