[MLIR] Omit version comment by default (#1313)

This change avoids having to update the version comment in gold files for every CIRCT upgrade.
phanrahan · Sep 21, 2023 · 2a34fa6 · 2a34fa6
1 parent 4387b64
commit 2a34fa6
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Showing 275 changed files with 186 additions and 301 deletions.
diff --git a/docs/split_verilog.md b/docs/split_verilog.md
@@ -56,7 +56,6 @@ m.compile("output/main", Top, output="mlir-verilog", **opts)
 ---
 `output/main.sv` (main RTL; note how it only includes `Bar`, `Foo`, and `Top`):
 ```Verilog
-// Generated by CIRCT circtorg-0.0.0-1018-g3a39b339f
 module Bar(
   input  [7:0] I,
   output [7:0] O);

diff --git a/magma/backend/mlir/compile_to_mlir_opts.py b/magma/backend/mlir/compile_to_mlir_opts.py
@@ -19,4 +19,4 @@ class CompileToMlirOpts:
     disallow_expression_inlining_in_ports: bool = False
     disallow_local_variables: bool = False
     split_verilog: bool = False
-    omit_version_comment: bool = False
+    omit_version_comment: bool = True
diff --git a/tests/gold/test_basic_namer_dict.mlir b/tests/gold/test_basic_namer_dict.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module.extern @Foo(%I: i8) -> (O: i8)
     hw.module @test_basic_namer_dict(%I: i8) -> (O: i8) {
         %1 = sv.wire sym @test_basic_namer_dict.x name "x" : !hw.inout<i8>

diff --git a/tests/gold/test_bind2_basic.mlir.tpl b/tests/gold/test_bind2_basic.mlir.tpl
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @TopBasicAsserts_mlir(%I: i1, %O: i1, %other: i1) -> () attributes {output_filelist = #hw.output_filelist<"$cwd/build/test_bind2_basic_bind_files.list">} {
     }
     hw.module @Top(%I: i1) -> (O: i1) {

diff --git a/tests/gold/test_bind2_basic_split_verilog.mlir.tpl b/tests/gold/test_bind2_basic_split_verilog.mlir.tpl
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @TopBasicAsserts_mlir(%I: i1, %O: i1, %other: i1) -> () attributes {output_file = #hw.output_file<"$cwd/build/TopBasicAsserts_mlir.v">, output_filelist = #hw.output_filelist<"$cwd/build/test_bind2_basic_split_verilog_bind_files.list">} {
     }
     hw.module @Top(%I: i1) -> (O: i1) attributes {output_file = #hw.output_file<"$cwd/build/test_bind2_basic_split_verilog.v">} {

diff --git a/tests/gold/test_bind2_generator.mlir.tpl b/tests/gold/test_bind2_generator.mlir.tpl
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @LogicAsserts(%I: i1, %O: i1, %other: i1) -> () attributes {output_filelist = #hw.output_filelist<"$cwd/build/test_bind2_generator_bind_files.list">} {
         sv.verbatim "{{0}} {{1}} {{2}}" (%I, %O, %other) : i1, i1, i1
     }

diff --git a/tests/gold/test_bind2_xmr.mlir.tpl b/tests/gold/test_bind2_xmr.mlir.tpl
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @Bottom(%I: !hw.struct<x: i1, y: i1>) -> (O: !hw.struct<x: i1, y: i1>) {
         hw.output %I : !hw.struct<x: i1, y: i1>
     }

diff --git a/tests/gold/test_bind2_xmr_flatten_all_tuples.mlir.tpl b/tests/gold/test_bind2_xmr_flatten_all_tuples.mlir.tpl
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @Bottom(%I_x: i1, %I_y: i1) -> (O_x: i1, O_y: i1) {
         hw.output %I_x, %I_y : i1, i1
     }

diff --git a/tests/gold/test_bind_basic_mlir.mlir b/tests/gold/test_bind_basic_mlir.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @Top(%I: i1) -> (O: i1) {
         %1 = sv.wire sym @Top._magma_bind_wire_0 name "_magma_bind_wire_0" : !hw.inout<i1>
         sv.assign %1, %I : i1

diff --git a/tests/gold/test_bind_xmr_mlir.mlir b/tests/gold/test_bind_xmr_mlir.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @Bottom(%I: i1) -> (O: i1) {
         hw.output %I : i1
     }

diff --git a/tests/gold/test_compile_guard_anon_driven_internal.mlir b/tests/gold/test_compile_guard_anon_driven_internal.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @COND_compile_guard(%port_0: i1) -> () {
         %1 = sv.wire sym @COND_compile_guard.corebit_undriven_inst0 : !hw.inout<i1>
         %0 = sv.read_inout %1 : !hw.inout<i1>

diff --git a/tests/gold/test_compile_guard_basic.mlir b/tests/gold/test_compile_guard_basic.mlir
diff --git a/tests/gold/test_compile_guard_inline_verilog_reset.mlir b/tests/gold/test_compile_guard_inline_verilog_reset.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @COND_compile_guard(%port_0: i1, %port_1: i1, %port_2: i1) -> () {
         sv.verbatim "\nassert property (@(posedge {{2}}) disable iff {{1}} {{0}} |-> ##1 {{0}};\n                " (%port_0, %port_1, %port_2) : i1, i1, i1
     }

diff --git a/tests/gold/test_inline_verilog2_share_default_clocks.mlir b/tests/gold/test_inline_verilog2_share_default_clocks.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @inline_verilog2_share_default_clocks(%x: i1, %y: i1, %CLK: i1, %RESET: i1) -> () {
         sv.verbatim "assert property (@(posedge {{0}}) disable iff (! {{1}}) {{2}} |-> ##1 {{3}});" (%CLK, %RESET, %x, %y) : i1, i1, i1, i1
         sv.verbatim "assert property (@(posedge {{0}}) disable iff (! {{1}}) {{2}} |-> ##1 {{3}});" (%CLK, %RESET, %x, %y) : i1, i1, i1, i1

diff --git a/tests/gold/test_inline_verilog2_simple.mlir b/tests/gold/test_inline_verilog2_simple.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @inline_verilog2_simple(%I: i1, %arr: i2, %CLK: i1) -> (O: i1) {
         %1 = sv.reg name "Register_inst0" : !hw.inout<i1>
         sv.alwaysff(posedge %CLK) {

diff --git a/tests/gold/test_inline_verilog2_tuple.mlir b/tests/gold/test_inline_verilog2_tuple.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module.extern @InnerInnerDelayUnit(%INPUT_0_data: i5, %INPUT_0_valid: i1, %INPUT_1_data: i5, %INPUT_1_valid: i1, %OUTPUT_0_ready: i1, %OUTPUT_1_ready: i1) -> (INPUT_0_ready: i1, INPUT_1_ready: i1, OUTPUT_0_data: i5, OUTPUT_0_valid: i1, OUTPUT_1_data: i5, OUTPUT_1_valid: i1)
     hw.module @InnerDelayUnit(%INPUT_0_data: i5, %INPUT_0_valid: i1, %INPUT_1_data: i5, %INPUT_1_valid: i1, %OUTPUT_0_ready: i1, %OUTPUT_1_ready: i1, %CLK: i1) -> (INPUT_0_ready: i1, INPUT_1_ready: i1, OUTPUT_0_data: i5, OUTPUT_0_valid: i1, OUTPUT_1_data: i5, OUTPUT_1_valid: i1) {
         %0, %1, %2, %3, %4, %5 = hw.instance "inner_inner_delay" @InnerInnerDelayUnit(INPUT_0_data: %INPUT_1_data: i5, INPUT_0_valid: %INPUT_1_valid: i1, INPUT_1_data: %INPUT_0_data: i5, INPUT_1_valid: %INPUT_0_valid: i1, OUTPUT_0_ready: %OUTPUT_1_ready: i1, OUTPUT_1_ready: %OUTPUT_0_ready: i1) -> (INPUT_0_ready: i1, INPUT_1_ready: i1, OUTPUT_0_data: i5, OUTPUT_0_valid: i1, OUTPUT_1_data: i5, OUTPUT_1_valid: i1)

diff --git a/tests/gold/test_inline_verilog2_uniquification.mlir b/tests/gold/test_inline_verilog2_uniquification.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @Foo(%I: i1) -> () {
         sv.verbatim "always @(*) $display(\"%d\\n\", {{0}});" (%I) : i1
     }

diff --git a/tests/gold/test_inline_verilog_expression_compilation_mlir.mlir b/tests/gold/test_inline_verilog_expression_compilation_mlir.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @MyWrapperGen_1(%I: i1, %CLK: i1) -> (O: i1) {
         %0 = sv.verbatim.expr "R | I" () : () -> (i1)
         sv.verbatim "reg [0:0] R;\nasssign R <= {{0}};\n" (%I) : i1

diff --git a/tests/gold/test_module_linking_no_default.mlir b/tests/gold/test_module_linking_no_default.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @_OrImpl(%I0: i1, %I1: i1) -> (O: i1) {
         %0 = comb.or %I0, %I1 : i1
         hw.output %0 : i1

diff --git a/tests/gold/test_module_linking_only_default.mlir b/tests/gold/test_module_linking_only_default.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @_OrImpl(%I0: i1, %I1: i1) -> (O: i1) {
         %0 = comb.or %I0, %I1 : i1
         hw.output %0 : i1

diff --git a/tests/gold/test_module_linking_with_default.mlir b/tests/gold/test_module_linking_with_default.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @_OrImpl(%I0: i1, %I1: i1) -> (O: i1) {
         %0 = comb.or %I0, %I1 : i1
         hw.output %0 : i1

diff --git a/tests/gold/test_namer_dict_already_named.mlir b/tests/gold/test_namer_dict_already_named.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module.extern @Foo(%I: i8) -> (O: i8)
     hw.module @test_namer_dict_already_named(%I: i8) -> (O: i8) {
         %1 = sv.wire sym @test_namer_dict_already_named.y name "y" : !hw.inout<i8>

diff --git a/tests/gold/test_namer_dict_explicit_collision_inst.mlir b/tests/gold/test_namer_dict_explicit_collision_inst.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module.extern @Foo(%I: i8) -> (O: i8)
     hw.module @test_namer_dict_explicit_collision_inst(%I: i8) -> (O: i8) {
         %0 = hw.instance "foo_0" @Foo(I: %I: i8) -> (O: i8)

diff --git a/tests/gold/test_namer_dict_explicit_collision_value.mlir b/tests/gold/test_namer_dict_explicit_collision_value.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_namer_dict_explicit_collision_value(%I: i8) -> (O: i8) {
         %1 = sv.wire sym @test_namer_dict_explicit_collision_value.y_0 name "y_0" : !hw.inout<i8>
         sv.assign %1, %I : i8

diff --git a/tests/gold/test_namer_dict_generator.mlir b/tests/gold/test_namer_dict_generator.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @Foo(%I: i8) -> (O: i8) {
         %1 = sv.wire sym @Foo.x name "x" : !hw.inout<i8>
         sv.assign %1, %I : i8

diff --git a/tests/gold/test_namer_dict_multiple.mlir b/tests/gold/test_namer_dict_multiple.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module.extern @Foo(%I: i8) -> (O: i8)
     hw.module @test_namer_dict_multiple(%I: i8) -> (O: i8) {
         %1 = sv.wire sym @test_namer_dict_multiple.x_0 name "x_0" : !hw.inout<i8>

diff --git a/tests/gold/test_namer_dict_smart_bits.mlir b/tests/gold/test_namer_dict_smart_bits.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_namer_dict_smart_bits(%I0: i8, %I1: i8) -> (O: i9) {
         %0 = comb.extract %I0 from 0 : (i8) -> i1
         %1 = comb.extract %I0 from 1 : (i8) -> i1

diff --git a/tests/gold/test_namer_dict_smart_bits_lazy.mlir b/tests/gold/test_namer_dict_smart_bits_lazy.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_namer_dict_smart_bits_lazy(%I0: i8, %I1: i8) -> (O: i9) {
         %0 = comb.extract %I0 from 0 : (i8) -> i1
         %1 = comb.extract %I0 from 1 : (i8) -> i1

diff --git a/tests/gold/test_namer_dict_smart_bits_lazy_rename.mlir b/tests/gold/test_namer_dict_smart_bits_lazy_rename.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_namer_dict_smart_bits_lazy_rename(%I0: i8, %I1: i8) -> (O: i9) {
         %0 = comb.extract %I0 from 0 : (i8) -> i1
         %1 = comb.extract %I0 from 1 : (i8) -> i1

diff --git a/tests/gold/test_test_inline_verilog2_clock_output.mlir b/tests/gold/test_test_inline_verilog2_clock_output.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_inline_verilog2_clock_output(%x: i1, %y: i1) -> () {
         sv.verbatim "Foo bar (.x({{0}}), .y({{1}}))" (%x, %y) : i1, i1
     }

diff --git a/tests/gold/test_test_inline_verilog2_passthrough_wire.mlir b/tests/gold/test_test_inline_verilog2_passthrough_wire.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_inline_verilog2_passthrough_wire(%I: !hw.struct<x: i1, y: i4>) -> (O: !hw.struct<x: i1, y: i4>) {
         %0 = hw.struct_extract %I["y"] : !hw.struct<x: i1, y: i4>
         %1 = comb.extract %0 from 0 : (i4) -> i1

diff --git a/tests/gold/test_test_inline_verilog2_wire_insertion_bad_verilog.mlir b/tests/gold/test_test_inline_verilog2_wire_insertion_bad_verilog.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_inline_verilog2_wire_insertion_bad_verilog(%I: i32) -> (O: i1) {
         %0 = comb.extract %I from 0 : (i32) -> i1
         sv.verbatim "`ifdef LOGGING_ON"

diff --git a/tests/gold/test_when_2d_array_assign.mlir b/tests/gold/test_when_2d_array_assign.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_2d_array_assign(%I: !hw.array<2xi2>, %S: i1) -> (O: !hw.array<2xi2>) {
         %1 = sv.reg : !hw.inout<!hw.array<2xi2>>
         %0 = sv.read_inout %1 : !hw.inout<!hw.array<2xi2>>

diff --git a/tests/gold/test_when_2d_array_assign_slice.mlir b/tests/gold/test_when_2d_array_assign_slice.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_2d_array_assign_slice(%I: !hw.array<4xi2>, %S: i1) -> (O: !hw.array<4xi2>) {
         %1 = sv.reg : !hw.inout<!hw.array<4xi2>>
         %0 = sv.read_inout %1 : !hw.inout<!hw.array<4xi2>>

diff --git a/tests/gold/test_when_3d_array_assign.mlir b/tests/gold/test_when_3d_array_assign.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_3d_array_assign(%I: !hw.array<2x!hw.array<2xi2>>, %S: i1) -> (O: !hw.array<2x!hw.array<2xi2>>) {
         %1 = sv.reg : !hw.inout<!hw.array<2x!hw.array<2xi2>>>
         %0 = sv.read_inout %1 : !hw.inout<!hw.array<2x!hw.array<2xi2>>>

diff --git a/tests/gold/test_when_array_3d_bulk_child.mlir b/tests/gold/test_when_array_3d_bulk_child.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_array_3d_bulk_child(%I: !hw.array<2x!hw.array<2xi2>>, %S: i1) -> (O: !hw.array<2x!hw.array<2xi2>>) {
         %1 = sv.reg : !hw.inout<!hw.array<2x!hw.array<2xi2>>>
         %0 = sv.read_inout %1 : !hw.inout<!hw.array<2x!hw.array<2xi2>>>

diff --git a/tests/gold/test_when_array_resolved_after.mlir b/tests/gold/test_when_array_resolved_after.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_array_resolved_after(%I: i8, %S: i1) -> (O: i16) {
         %0 = hw.constant 0 : i1
         %1 = hw.constant 0 : i1

diff --git a/tests/gold/test_when_double_elsewhen.mlir b/tests/gold/test_when_double_elsewhen.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_double_elsewhen(%I: i2, %S: i2) -> (O: i1) {
         %0 = comb.extract %S from 0 : (i2) -> i1
         %1 = comb.extract %I from 0 : (i2) -> i1

diff --git a/tests/gold/test_when_else.mlir b/tests/gold/test_when_else.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_else(%I: i2, %S: i1) -> (O: i1) {
         %0 = comb.extract %I from 0 : (i2) -> i1
         %1 = comb.extract %I from 1 : (i2) -> i1

diff --git a/tests/gold/test_when_elsewhen.mlir b/tests/gold/test_when_elsewhen.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_elsewhen(%I: i3, %S: i2) -> (O: i1) {
         %0 = comb.extract %S from 0 : (i2) -> i1
         %1 = comb.extract %I from 0 : (i3) -> i1

diff --git a/tests/gold/test_when_emit_asserts_basic.mlir b/tests/gold/test_when_emit_asserts_basic.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_emit_asserts_basic(%I: i2, %S: i1) -> (O: i1) {
         %0 = comb.extract %I from 1 : (i2) -> i1
         %1 = comb.extract %I from 0 : (i2) -> i1

diff --git a/tests/gold/test_when_emit_asserts_chained.mlir b/tests/gold/test_when_emit_asserts_chained.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_emit_asserts_chained(%I: i2, %S: i2) -> (O: i1) {
         %0 = comb.extract %S from 1 : (i2) -> i1
         %1 = comb.extract %S from 0 : (i2) -> i1

diff --git a/tests/gold/test_when_emit_asserts_elsewhen.mlir b/tests/gold/test_when_emit_asserts_elsewhen.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_emit_asserts_elsewhen(%I: i2, %S: i2) -> (O: i1) {
         %0 = comb.extract %S from 0 : (i2) -> i1
         %1 = comb.extract %I from 1 : (i2) -> i1

diff --git a/tests/gold/test_when_emit_asserts_elsewhen_otherwise.mlir b/tests/gold/test_when_emit_asserts_elsewhen_otherwise.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_emit_asserts_elsewhen_otherwise(%I: i2, %S: i2) -> (O: i1) {
         %0 = comb.extract %S from 0 : (i2) -> i1
         %1 = comb.extract %I from 0 : (i2) -> i1

diff --git a/tests/gold/test_when_emit_asserts_nesting.mlir b/tests/gold/test_when_emit_asserts_nesting.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_emit_asserts_nesting(%I: i2, %S: i2) -> (O: i1) {
         %0 = comb.extract %S from 0 : (i2) -> i1
         %1 = comb.extract %S from 1 : (i2) -> i1

diff --git a/tests/gold/test_when_emit_asserts_otherwise.mlir b/tests/gold/test_when_emit_asserts_otherwise.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_emit_asserts_otherwise(%I: i2, %S: i1) -> (O: i1) {
         %0 = comb.extract %I from 0 : (i2) -> i1
         %1 = comb.extract %I from 1 : (i2) -> i1

diff --git a/tests/gold/test_when_emit_asserts_tuple.mlir b/tests/gold/test_when_emit_asserts_tuple.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_emit_asserts_tuple(%I_0_0: i8, %I_0_1: i1, %I_1_0: i8, %I_1_1: i1, %S: i1) -> (O_0: i8, O_1: i1) {
         %2 = sv.reg : !hw.inout<i8>
         %0 = sv.read_inout %2 : !hw.inout<i8>

diff --git a/tests/gold/test_when_emit_asserts_tuple_elab.mlir b/tests/gold/test_when_emit_asserts_tuple_elab.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_emit_asserts_tuple_elab(%I_0_0: i8, %I_0_1: i1, %I_1_0: i8, %I_1_1: i1, %S: i1, %CLK: i1) -> (O_0: i8, O_1: i1) {
         %4 = sv.reg : !hw.inout<i8>
         %2 = sv.read_inout %4 : !hw.inout<i8>

diff --git a/tests/gold/test_when_emit_asserts_value.mlir b/tests/gold/test_when_emit_asserts_value.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_emit_asserts_value(%S: i3, %O_ready: i1, %CLK: i1) -> (O_valid: i1, O_data_x: i1, O_data_y: i8) {
         %0 = hw.constant 0 : i1
         %1 = comb.extract %S from 0 : (i3) -> i1

diff --git a/tests/gold/test_when_internal_instantiation.mlir b/tests/gold/test_when_internal_instantiation.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_internal_instantiation(%I: i2, %S: i1) -> (O: i1) {
         %0 = comb.extract %I from 0 : (i2) -> i1
         %1 = hw.constant 1 : i1

diff --git a/tests/gold/test_when_lazy_array.mlir b/tests/gold/test_when_lazy_array.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_lazy_array(%S: i1) -> (O: i2) {
         %0 = hw.constant 0 : i1
         %1 = hw.constant 1 : i1

diff --git a/tests/gold/test_when_lazy_array_multiple_whens.mlir b/tests/gold/test_when_lazy_array_multiple_whens.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_lazy_array_multiple_whens(%I: i4, %S: i1) -> (O: i4) {
         %1 = hw.constant -1 : i1
         %0 = comb.xor %1, %S : i1

diff --git a/tests/gold/test_when_lazy_array_nested.mlir b/tests/gold/test_when_lazy_array_nested.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_lazy_array_nested(%S: i1) -> (O: !hw.array<2x!hw.struct<x: i1, y: i1>>) {
         %0 = hw.constant 0 : i1
         %1 = hw.constant 1 : i1

diff --git a/tests/gold/test_when_lazy_array_protocol.mlir b/tests/gold/test_when_lazy_array_protocol.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_lazy_array_protocol(%S: i1) -> (O: !hw.array<2xi1>) {
         %0 = hw.constant 0 : i1
         %1 = hw.constant 1 : i1

diff --git a/tests/gold/test_when_lazy_array_resolve.mlir b/tests/gold/test_when_lazy_array_resolve.mlir
@@ -1,4 +1,4 @@
-module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
+module attributes {circt.loweringOptions = "locationInfoStyle=none,omitVersionComment"} {
     hw.module @test_when_lazy_array_resolve(%I: i2, %S: i1) -> (O: i2) {
         %0 = hw.constant 1 : i2
         %1 = comb.shru %I, %0 : i2