Altera 5.4 #1
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Altera 5.4 #1
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Imported from altera_4.14 branch.
fpga_mgr uses dma-buf as well, so select the DMA_SHARED_BUFFER config to fix below compilation errors that require this config enabled. drivers/fpga/fpga-mgr.o: In function `fpga_dmabuf_fd_get': /home/soceds/datastorm_daq/adrv9002_linux/drivers/fpga/fpga-mgr.c:693: undefined reference to `dma_buf_get' drivers/fpga/fpga-mgr.o: In function `fpga_dmabuf_load': /home/soceds/datastorm_daq/adrv9002_linux/drivers/fpga/fpga-mgr.c:315: undefined reference to `dma_buf_attach' /home/soceds/datastorm_daq/adrv9002_linux/drivers/fpga/fpga-mgr.c:322: undefined reference to `dma_buf_map_attachment' /home/soceds/datastorm_daq/adrv9002_linux/drivers/fpga/fpga-mgr.c:330: undefined reference to `dma_buf_unmap_attachment' /home/soceds/datastorm_daq/adrv9002_linux/drivers/fpga/fpga-mgr.c:333: undefined reference to `dma_buf_detach' /home/soceds/datastorm_daq/adrv9002_linux/drivers/fpga/fpga-mgr.c:335: undefined reference to `dma_buf_put' Signed-off-by: d-samal <[email protected]>
- Import Arria 10 specific defconfig from altera_4.14 branch - Update DTS to include proper addressing and nodes Signed-off-by: d-samal <[email protected]>
- Added mising nodes in DTS - Imported existing defconfig for Linux v5.4 for socfpga Signed-off-by: d-samal <[email protected]>
Ethernet drivers require the Altera System Manager drivers which are not enabled by default from 5.x kernels. The current socfpga_adi_defconfig is based on the 4.14 kernels which does not need this config to start the syscon drivers. Hence, adding the MFD_ALTERA_SYSMGR config in the defconfig to enable the SOCFPGA System Manager drivers in kernel and enable ethernet properly by fixing the following errors. socfpga-dwmac ff802000.ethernet: No sysmgr-syscon node found socfpga-dwmac ff802000.ethernet: Unable to parse OF data Signed-off-by: d-samal <[email protected]>
Update addresses and interrupts specific for ADRV9002 according the HDL hardware design. Signed-off-by: d-samal <[email protected]>
This driver includes a case for 2-Lane mode that is utilized only in LVDS-LSSI mode since CMOS-CSSI only has 1-Lane and 4-Lane modes of operation. Change the rate config up to 7 for LVDS 2-Lane mode in accordance to the HDL hardware design for synced tx and rx operations. Signed-off-by: d-samal <[email protected]>
Use long strobe by default for all LVDS configurations. Signed-off-by: d-samal <[email protected]>
Update rate configuration in accordance to HDL design for CMOS 4-Lane DDR mode operation in ADRV9002. Signed-off-by: d-samal <[email protected]>
MitySOM A10s seems to have tuning bootup errors even though there are no data acquisition errors in ADRV9002. Apply this patch file to set the delay values to driver defaults since the same test pattern is used for caliberations. This not a long term patch, needs to be fixed and reverted once HDL does not need this patch. Signed-off-by: d-samal <[email protected]>
TES SDK15. Supports B0 and C0 devices
commit 0dcabf4 5/21/2021 for analogdevicesinc/linux repository. API now compatible with SDK15 ( revision 45.0.5).
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