Skip to content

Commit

Permalink
modules: microchip: MEC15xx Add missing eSPI VW definitions
Browse files Browse the repository at this point in the history 
Add missing eSPI MSVW08 - MSVW11 definitions.
Update GPIO ID enum with max value.
Remove non-printable character from SAF header.
Make sure all structure typedefs have a structure name.
Rename SPISLV to SPIP.
Changed all hex digits to lowe case.
Converted all "ul/UL" suffixes to "u".

Signed-off-by: Scott Worley <[email protected]>
  • Loading branch information
@scottwcpg
scottwcpg committed Jul 26, 2021
1 parent ff0a329 commit 870d05e
Show file tree
Hide file tree
Showing 38 changed files with 2,946 additions and 2,790 deletions.
9 changes: 9 additions & 0 deletions README.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,3 +15,12 @@ https://github.com/MicrochipTech/hal_microchip

Version: 1.2.1
Add missing eSPI Virtual Wires groups 8 - 10 GIRQ definitions.
Make sure all typedef's of structures are "typedef struct struct_name".
Remove non-printable character from SAF header
Add max name to GPIO ID enum
Rename the SPISLV to SPIP

Version: 1.2.1
Update eSPI definitions
Changed all hex upper case 'ABCDEF' to lower case
Changed all 'ul/UL' unsigned numeric suffix to 'u'
252 changes: 126 additions & 126 deletions mec/mec1501/MEC1501hsz.h
View file

Large diffs are not rendered by default.

186 changes: 92 additions & 94 deletions mec/mec1501/component/acpi_ec.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,16 +42,16 @@
/* ================ ACPI_EC =================== */
/* =========================================================================*/

#define MCHP_ACPI_EC_BASE_ADDR 0x400F0800ul
#define MCHP_ACPI_EC_BASE_ADDR 0x400f0800u

#define MCHP_ACPI_EC_NUM_INSTANCES 4u
#define MCHP_ACPI_EC_SPACING 0x0400ul
#define MCHP_ACPI_EC_SPACING 0x0400u
#define MCHP_ACPI_EC_SPACING_PWROF2 10u

#define MCHP_ACPI_EC0_ADDR 0x400F0800ul
#define MCHP_ACPI_EC1_ADDR 0x400F0C00ul
#define MCHP_ACPI_EC2_ADDR 0x400F1000ul
#define MCHP_ACPI_EC3_ADDR 0x400F1400ul
#define MCHP_ACPI_EC0_ADDR 0x400f0800u
#define MCHP_ACPI_EC1_ADDR 0x400f0C00u
#define MCHP_ACPI_EC2_ADDR 0x400f1000u
#define MCHP_ACPI_EC3_ADDR 0x400f1400u

/* 0 <= n < MCHP_ACPI_EC_NUM_INSTANCES */
#define MCHP_ACPI_EC_ADDR(n) (MCHP_ACPI_EC_BASE_ADDR +\
Expand All @@ -67,64 +67,64 @@
#define MCHP_ACPI_EC_0_OBE_NVIC 46u
#define MCHP_ACPI_EC_0_IBF_GIRQ_POS 5u
#define MCHP_ACPI_EC_0_OBE_GIRQ_POS 6u
#define MCHP_ACPI_EC_0_IBF_GIRQ (1ul << 5)
#define MCHP_ACPI_EC_0_OBE_GIRQ (1ul << 6)
#define MCHP_ACPI_EC_0_IBF_GIRQ BIT(5)
#define MCHP_ACPI_EC_0_OBE_GIRQ BIT(6)

#define MCHP_ACPI_EC_1_IBF_NVIC 47u
#define MCHP_ACPI_EC_1_OBE_NVIC 48u
#define MCHP_ACPI_EC_1_IBF_GIRQ_POS 7u
#define MCHP_ACPI_EC_1_OBE_GIRQ_POS 8u
#define MCHP_ACPI_EC_1_IBF_GIRQ (1ul << 7)
#define MCHP_ACPI_EC_1_OBE_GIRQ (1ul << 8)
#define MCHP_ACPI_EC_1_IBF_GIRQ BIT(7)
#define MCHP_ACPI_EC_1_OBE_GIRQ BIT(8)

#define MCHP_ACPI_EC_2_IBF_NVIC 49u
#define MCHP_ACPI_EC_2_OBE_NVIC 50u
#define MCHP_ACPI_EC_2_IBF_GIRQ_POS 9u
#define MCHP_ACPI_EC_2_OBE_GIRQ_POS 10u
#define MCHP_ACPI_EC_2_IBF_GIRQ (1ul << 9)
#define MCHP_ACPI_EC_2_OBE_GIRQ (1ul << 10)
#define MCHP_ACPI_EC_2_IBF_GIRQ BIT(9)
#define MCHP_ACPI_EC_2_OBE_GIRQ BIT(10)

#define MCHP_ACPI_EC_3_IBF_NVIC 51u
#define MCHP_ACPI_EC_3_OBE_NVIC 52u
#define MCHP_ACPI_EC_3_IBF_GIRQ_POS 11u
#define MCHP_ACPI_EC_3_OBE_GIRQ_POS 12u
#define MCHP_ACPI_EC_3_IBF_GIRQ (1ul << 11)
#define MCHP_ACPI_EC_3_OBE_GIRQ (1ul << 12)
#define MCHP_ACPI_EC_3_IBF_GIRQ BIT(11)
#define MCHP_ACPI_EC_3_OBE_GIRQ BIT(12)

/* 0 <= n < MCHP_ACPI_EC_NUM_INSTANCES */
#define MCHP_ACPI_EC_IBF_NVIC(n) (45ul + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_OBE_NVIC(n) (46ul + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_IBF_GIRQ_POS(n) (5ul + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_OBE_GIRQ_POS(n) (6ul + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_IBF_GIRQ(n) (1ul << MCHP_ACPI_EC_IBF_GIRQ_POS(n))
#define MCHP_ACPI_EC_OBE_GIRQ(n) (1ul << MCHP_ACPI_EC_OBE_GIRQ_POS(n))
#define MCHP_ACPI_EC_IBF_NVIC(n) (45u + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_OBE_NVIC(n) (46u + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_IBF_GIRQ_POS(n) (5u + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_OBE_GIRQ_POS(n) (6u + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_IBF_GIRQ(n) (1u << MCHP_ACPI_EC_IBF_GIRQ_POS(n))
#define MCHP_ACPI_EC_OBE_GIRQ(n) (1u << MCHP_ACPI_EC_OBE_GIRQ_POS(n))


/*
* EC_STS and OS_CMD_STS(read) bit definitions
*/
#define MCHP_ACPI_EC_STS_OBF_POS 0u
#define MCHP_ACPI_EC_STS_OBF (1ul << (MCHP_ACPI_EC_STS_OBF_POS))
#define MCHP_ACPI_EC_STS_OBF BIT(MCHP_ACPI_EC_STS_OBF_POS)
#define MCHP_ACPI_EC_STS_IBF_POS 1u
#define MCHP_ACPI_EC_STS_IBF (1ul << (MCHP_ACPI_EC_STS_IBF_POS))
#define MCHP_ACPI_EC_STS_IBF BIT(MCHP_ACPI_EC_STS_IBF_POS)
#define MCHP_ACPI_EC_STS_UD1A_POS 2u
#define MCHP_ACPI_EC_STS_UD1A (1ul << (MCHP_ACPI_EC_STS_UD1A_POS))
#define MCHP_ACPI_EC_STS_UD1A BIT(MCHP_ACPI_EC_STS_UD1A_POS)
#define MCHP_ACPI_EC_STS_CMD_POS 3u
#define MCHP_ACPI_EC_STS_CMD (1ul << (MCHP_ACPI_EC_STS_CMD_POS))
#define MCHP_ACPI_EC_STS_CMD BIT(MCHP_ACPI_EC_STS_CMD_POS)
#define MCHP_ACPI_EC_STS_BURST_POS 4u
#define MCHP_ACPI_EC_STS_BURST (1ul << (MCHP_ACPI_EC_STS_BURST_POS))
#define MCHP_ACPI_EC_STS_BURST BIT(MCHP_ACPI_EC_STS_BURST_POS)
#define MCHP_ACPI_EC_STS_SCI_POS 5u
#define MCHP_ACPI_EC_STS_SCI (1ul << (MCHP_ACPI_EC_STS_SCI_POS))
#define MCHP_ACPI_EC_STS_SCI BIT(MCHP_ACPI_EC_STS_SCI_POS)
#define MCHP_ACPI_EC_STS_SMI_POS 6u
#define MCHP_ACPI_EC_STS_SMI (1ul << (MCHP_ACPI_EC_STS_SMI_POS))
#define MCHP_ACPI_EC_STS_SMI BIT(MCHP_ACPI_EC_STS_SMI_POS)
#define MCHP_ACPI_EC_STS_UD0A_POS 7u
#define MCHP_ACPI_EC_STS_UD0A (1ul << (MCHP_ACPI_EC_STS_UD0A_POS))
#define MCHP_ACPI_EC_STS_UD0A BIT(MCHP_ACPI_EC_STS_UD0A_POS)

/*
* EC_BYTE_CTRL and OS_BYTE_CTRL
*/
#define MCHP_ACPI_EC_BYTE_CTRL_4B_POS 0u
#define MCHP_ACPI_EC_BYTE_CTRL_4B_EN (1ul << (MCHP_ACPI_EC_BYTE_CTRL_4B_POS))
#define MCHP_ACPI_EC_BYTE_CTRL_4B_EN BIT(MCHP_ACPI_EC_BYTE_CTRL_4B_POS)

/**
* @brief ACPI EC Registers (ACPI_EC)
Expand All @@ -133,7 +133,7 @@ typedef struct acpi_ec_regs {
__IOM uint32_t OS_DATA; /*!< (@ 0x0000) OS Data */
__IOM uint8_t OS_CMD_STS; /*!< (@ 0x0004) OS Command(WO), Status(RO) */
__IOM uint8_t OS_BYTE_CTRL; /*!< (@ 0x0005) OS Byte Control */
uint8_t RSVD1[0x100u - 0x06u];
uint8_t RSVD1[0x100 - 0x06];
__IOM uint32_t EC2OS_DATA; /*!< (@ 0x0100) EC to OS Data */
__IOM uint8_t EC_STS; /*!< (@ 0x0104) EC Status */
__IOM uint8_t EC_BYTE_CTRL; /*!< (@ 0x0105) EC Byte Control */
Expand All @@ -145,7 +145,7 @@ typedef struct acpi_ec_regs {
/* ================ ACPI_PM1 =================== */
/* =========================================================================*/

#define MCHP_ACPI_PM1_BASE_ADDR 0x400F1C00ul
#define MCHP_ACPI_PM1_BASE_ADDR 0x400f1c00u

/*
* ACPI_PM1 interrupts
Expand All @@ -159,9 +159,9 @@ typedef struct acpi_ec_regs {
#define MCHP_ACPI_PM1_EN_GIRQ_POS 16u
#define MCHP_ACPI_PM1_STS_GIRQ_POS 17u

#define MCHP_ACPI_PM1_CTL_GIRQ_VAL (1ul << MCHP_ACPI_PM1_CTL_GIRQ_POS)
#define MCHP_ACPI_PM1_EN_GIRQ_VAL (1ul << MCHP_ACPI_PM1_EN_GIRQ_POS)
#define MCHP_ACPI_PM1_STS_GIRQ_VAL (1ul << MCHP_ACPI_PM1_STS_GIRQ_POS)
#define MCHP_ACPI_PM1_CTL_GIRQ_VAL BIT(MCHP_ACPI_PM1_CTL_GIRQ_POS)
#define MCHP_ACPI_PM1_EN_GIRQ_VAL BIT(MCHP_ACPI_PM1_EN_GIRQ_POS)
#define MCHP_ACPI_PM1_STS_GIRQ_VAL BIT(MCHP_ACPI_PM1_STS_GIRQ_POS)

/* VCI GIRQ aggregated NVIC input */
#define MCHP_ACPI_PM1_CTL_NVIC_AGGR 7u
Expand All @@ -174,85 +174,83 @@ typedef struct acpi_ec_regs {
#define MCHP_ACPI_PM1_STS_NVIC_DIRECT 57u

/* ACPI_PM1 RT/EC Status 1 */
#define MCHP_ACPI_PM1_RT_STS1_REG_OFS 0x0000ul
#define MCHP_ACPI_PM1_EC_STS1_REG_OFS 0x0100ul
#define MCHP_ACPI_PM1_STS1_REG_MASK 0x0000ul
#define MCHP_ACPI_PM1_RT_STS1_REG_OFS 0u
#define MCHP_ACPI_PM1_EC_STS1_REG_OFS 0x0100u
#define MCHP_ACPI_PM1_STS1_REG_MASK 0u

/* ACPI_PM1 RT/EC Status 2 */
#define MCHP_ACPI_PM1_RT_STS2_REG_OFS 0x0001ul
#define MCHP_ACPI_PM1_EC_STS2_REG_OFS 0x0101ul
#define MCHP_ACPI_PM1_STS2_REG_MASK 0x008Ful
#define MCHP_ACPI_PM1_STS2_PWRBTN (1ul << 0)
#define MCHP_ACPI_PM1_STS2_SLPBTN (1ul << 1)
#define MCHP_ACPI_PM1_STS2_RTC (1ul << 2)
#define MCHP_ACPI_PM1_STS2_PWRBTNOR (1ul << 3)
#define MCHP_ACPI_PM1_STS2_WAK (1ul << 7)
#define MCHP_ACPI_PM1_RT_STS2_REG_OFS 0x0001u
#define MCHP_ACPI_PM1_EC_STS2_REG_OFS 0x0101u
#define MCHP_ACPI_PM1_STS2_REG_MASK 0x008fu
#define MCHP_ACPI_PM1_STS2_PWRBTN BIT(0)
#define MCHP_ACPI_PM1_STS2_SLPBTN BIT(1)
#define MCHP_ACPI_PM1_STS2_RTC BIT(2)
#define MCHP_ACPI_PM1_STS2_PWRBTNOR BIT(3)
#define MCHP_ACPI_PM1_STS2_WAK BIT(7)

/* ACPI_PM1 RT/EC Enable 1 */
#define MCHP_ACPI_PM1_RT_EN1_REG_OFS 0x0002ul
#define MCHP_ACPI_PM1_EC_EN1_REG_OFS 0x0102ul
#define MCHP_ACPI_PM1_EN1_REG_MASK 0x0000ul
#define MCHP_ACPI_PM1_RT_EN1_REG_OFS 0x0002u
#define MCHP_ACPI_PM1_EC_EN1_REG_OFS 0x0102u
#define MCHP_ACPI_PM1_EN1_REG_MASK 0u

/* ACPI_PM1 RT/EC Enable 2 */
#define MCHP_ACPI_PM1_RT_EN2_REG_OFS 0x0003ul
#define MCHP_ACPI_PM1_EC_EN2_REG_OFS 0x0103ul
#define MCHP_ACPI_PM1_EN2_REG_MASK 0x0007ul
#define MCHP_ACPI_PM1_EN2_PWRBTN (1ul << 0)
#define MCHP_ACPI_PM1_EN2_SLPBTN (1ul << 1)
#define MCHP_ACPI_PM1_EN2_RTC (1ul << 2)
#define MCHP_ACPI_PM1_RT_EN2_REG_OFS 0x0003u
#define MCHP_ACPI_PM1_EC_EN2_REG_OFS 0x0103u
#define MCHP_ACPI_PM1_EN2_REG_MASK 0x0007u
#define MCHP_ACPI_PM1_EN2_PWRBTN BIT(0)
#define MCHP_ACPI_PM1_EN2_SLPBTN BIT(1)
#define MCHP_ACPI_PM1_EN2_RTC BIT(2)

/* ACPI_PM1 RT/EC Control 1 */
#define MCHP_ACPI_PM1_RT_CTRL1_REG_OFS 0x0004ul
#define MCHP_ACPI_PM1_EC_CTRL1_REG_OFS 0x0104ul
#define MCHP_ACPI_PM1_CTRL1_REG_MASK 0x0000ul
#define MCHP_ACPI_PM1_RT_CTRL1_REG_OFS 0x0004u
#define MCHP_ACPI_PM1_EC_CTRL1_REG_OFS 0x0104u
#define MCHP_ACPI_PM1_CTRL1_REG_MASK 0u

/* ACPI_PM1 RT/EC Control 2 */
#define MCHP_ACPI_PM1_RT_CTRL2_REG_OFS 0x0005ul
#define MCHP_ACPI_PM1_EC_CTRL2_REG_OFS 0x0105ul
#define MCHP_ACPI_PM1_CTRL2_REG_MASK 0x003Eul
#define MCHP_ACPI_PM1_CTRL2_PWRBTNOR_EN (1ul << 1)
#define MCHP_ACPI_PM1_RT_CTRL2_REG_OFS 0x0005u
#define MCHP_ACPI_PM1_EC_CTRL2_REG_OFS 0x0105u
#define MCHP_ACPI_PM1_CTRL2_REG_MASK 0x003eu
#define MCHP_ACPI_PM1_CTRL2_PWRBTNOR_EN BIT(1)
#define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_POS 2
#define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_MASK (0x03ul << 2)
#define MCHP_ACPI_PM1_CTRL2_SLP_EN (1ul << 5)
#define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_MASK (0x03u << 2)
#define MCHP_ACPI_PM1_CTRL2_SLP_EN BIT(5)

/* ACPI_PM1 RT/EC Control 21 */
#define MCHP_ACPI_PM1_RT_CTRL21_REG_OFS 0x0006ul
#define MCHP_ACPI_PM1_EC_CTRL21_REG_OFS 0x0106ul
#define MCHP_ACPI_PM1_CTRL21_REG_MASK 0x0000ul
#define MCHP_ACPI_PM1_RT_CTRL21_REG_OFS 0x0006u
#define MCHP_ACPI_PM1_EC_CTRL21_REG_OFS 0x0106u
#define MCHP_ACPI_PM1_CTRL21_REG_MASK 0u

/* ACPI_PM1 RT/EC Control 22 */
#define MCHP_ACPI_PM1_RT_CTRL22_REG_OFS 0x0007ul
#define MCHP_ACPI_PM1_EC_CTRL22_REG_OFS 0x0107ul
#define MCHP_ACPI_PM1_CTRL22_REG_MASK 0x0000ul
#define MCHP_ACPI_PM1_RT_CTRL22_REG_OFS 0x0007u
#define MCHP_ACPI_PM1_EC_CTRL22_REG_OFS 0x0107u
#define MCHP_ACPI_PM1_CTRL22_REG_MASK 0u

/* ACPI_PM1 EC PM Status register */
#define MCHP_ACPI_PM1_EC_PM_STS_REG_OFS 0x0110ul
#define MCHP_ACPI_PM1_EC_PM_STS_REG_MASK 0x0001ul
#define MCHP_ACPI_PM1_EC_PM_STS_SCI 0x0001ul
#define MCHP_ACPI_PM1_EC_PM_STS_REG_OFS 0x0110u
#define MCHP_ACPI_PM1_EC_PM_STS_REG_MASK 0x0001u
#define MCHP_ACPI_PM1_EC_PM_STS_SCI 0x0001u

/**
* @brief ACPI PM1 Registers (ACPI_PM1)
*/
/** @brief ACPI PM1 Registers (ACPI_PM1) */
typedef struct acpi_pm1_regs {
__IOM uint8_t RT_STS1; /*!< (@ 0x0000) */
__IOM uint8_t RT_STS2; /*!< (@ 0x0001) */
__IOM uint8_t RT_EN1; /*!< (@ 0x0002) */
__IOM uint8_t RT_EN2; /*!< (@ 0x0003) */
__IOM uint8_t RT_CTRL1; /*!< (@ 0x0004) */
__IOM uint8_t RT_CTRL2; /*!< (@ 0x0005) */
__IOM uint8_t RT_CTRL21; /*!< (@ 0x0006) */
__IOM uint8_t RT_CTRL22; /*!< (@ 0x0007) */
uint8_t RSVD1[(0x100u - 0x008u)];
__IOM uint8_t EC_STS1; /*!< (@ 0x0100) */
__IOM uint8_t EC_STS2; /*!< (@ 0x0101) */
__IOM uint8_t EC_EN1; /*!< (@ 0x0102) */
__IOM uint8_t EC_EN2; /*!< (@ 0x0103) */
__IOM uint8_t EC_CTRL1; /*!< (@ 0x0104) */
__IOM uint8_t EC_CTRL2; /*!< (@ 0x0105) */
__IOM uint8_t EC_CTRL21; /*!< (@ 0x0106) */
__IOM uint8_t EC_CTRL22; /*!< (@ 0x0107) */
uint8_t RSVD2[(0x0110u - 0x0108u)];
__IOM uint8_t EC_PM_STS; /*!< (@ 0x0110) */
__IOM uint8_t RT_STS1; /*!< (@ 0x0000) */
__IOM uint8_t RT_STS2; /*!< (@ 0x0001) */
__IOM uint8_t RT_EN1; /*!< (@ 0x0002) */
__IOM uint8_t RT_EN2; /*!< (@ 0x0003) */
__IOM uint8_t RT_CTRL1; /*!< (@ 0x0004) */
__IOM uint8_t RT_CTRL2; /*!< (@ 0x0005) */
__IOM uint8_t RT_CTRL21; /*!< (@ 0x0006) */
__IOM uint8_t RT_CTRL22; /*!< (@ 0x0007) */
uint8_t RSVD1[(0x100 - 0x008)];
__IOM uint8_t EC_STS1; /*!< (@ 0x0100) */
__IOM uint8_t EC_STS2; /*!< (@ 0x0101) */
__IOM uint8_t EC_EN1; /*!< (@ 0x0102) */
__IOM uint8_t EC_EN2; /*!< (@ 0x0103) */
__IOM uint8_t EC_CTRL1; /*!< (@ 0x0104) */
__IOM uint8_t EC_CTRL2; /*!< (@ 0x0105) */
__IOM uint8_t EC_CTRL21; /*!< (@ 0x0106) */
__IOM uint8_t EC_CTRL22; /*!< (@ 0x0107) */
uint8_t RSVD2[(0x0110 - 0x0108)];
__IOM uint8_t EC_PM_STS; /*!< (@ 0x0110) */
uint8_t RSVD3[3];
} ACPI_PM1_Type;

Expand Down
Loading

0 comments on commit 870d05e

Please sign in to comment.