6v misc

docs/xilinx/virtex6/center.rst

@@ -0,0 +1,20 @@
+.. _virtex6-center:
+
+Configuration Center
+####################
+
+.. todo:: document
+
+
+Bitstream
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-CFG.html
+
+
+Bitstream — PMVIOB
+==================
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-PMVIOB.html

docs/xilinx/virtex6/config.rst

@@ -0,0 +1,61 @@
+.. _virtex6-config:
+
+Configuration registers
+#######################
+
+.. todo:: document
+
+``COR``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-REG.COR.html
+
+
+``COR1``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-REG.COR1.html
+
+
+``CTL``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-REG.CTL.html
+
+
+``CTL1``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-REG.CTL1.html
+
+
+``TIMER``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-REG.TIMER.html
+
+
+``TESTMODE``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-REG.TESTMODE.html
+
+
+``TRIM``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-REG.TRIM.html
+
+
+``UNK1C``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-REG.UNK1C.html

docs/xilinx/virtex6/index.rst

@@ -11,5 +11,7 @@ Virtex 6
    clb
    bram
    dsp
+   center
    emac
    pcie
+   config

prjcombine_ise_hammer/src/backend.rs

@@ -148,6 +148,12 @@ pub struct FeatureBit {
     pub bit: usize,
 }
 
+impl FeatureBit {
+    pub fn new(tile: usize, frame: usize, bit: usize) -> Self {
+        Self { tile, frame, bit }
+    }
+}
+
 impl core::fmt::Debug for FeatureBit {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         write!(f, "{}.{}.{}", self.tile, self.frame, self.bit)

prjcombine_ise_hammer/src/fgen.rs

@@ -1607,6 +1607,7 @@ pub enum TileBits {
     Null,
     Main(usize),
     Reg(Reg),
+    RegPresent(Reg),
     Raw(Vec<BitTile>),
     MainUp,
     MainDown,
@@ -2098,6 +2099,12 @@ impl TileBits {
                     BitTile::RegPresent(die, Reg::FakeFreezeDciNops),
                 ]
             }
+            TileBits::RegPresent(reg) => {
+                vec![
+                    BitTile::Reg(die, reg),
+                    BitTile::RegPresent(die, reg),
+                ]
+            }
             TileBits::Pcie => {
                 let ExpandedDevice::Virtex4(edev) = backend.edev else {
                     unreachable!()
@@ -2142,7 +2149,7 @@ pub enum ExtraFeatureKind {
     MgtRepeater(Dir, Option<Dir>),
     BufpllPll(Dir, &'static str),
     Reg(Reg),
-    HclkIoiTopCen,
+    HclkSysmonDrp,
     HclkIoiCenter(&'static str),
     HclkBramMgtPrev,
     PcieHclk,
@@ -2373,11 +2380,20 @@ impl ExtraFeatureKind {
                 .ids()
                 .map(|die| vec![BitTile::Reg(die, reg)])
                 .collect(),
-            ExtraFeatureKind::HclkIoiTopCen => {
+            ExtraFeatureKind::HclkSysmonDrp => {
                 let ExpandedDevice::Virtex4(edev) = backend.edev else {
                     unreachable!()
                 };
-                vec![vec![edev.btile_hclk(loc.0, loc.1, loc.2 + 20)]]
+                match edev.kind {
+                    prjcombine_virtex4::grid::GridKind::Virtex4 => todo!(),
+                    prjcombine_virtex4::grid::GridKind::Virtex5 => {
+                        vec![vec![edev.btile_hclk(loc.0, loc.1, loc.2 + 20)]]
+                    }
+                    prjcombine_virtex4::grid::GridKind::Virtex6 => {
+                        vec![vec![edev.btile_hclk(loc.0, loc.1, loc.2 + 20)]]
+                    }
+                    prjcombine_virtex4::grid::GridKind::Virtex7 => todo!(),
+                }
             }
             ExtraFeatureKind::HclkIoiCenter(kind) => {
                 let ExpandedDevice::Virtex4(edev) = backend.edev else {

prjcombine_ise_hammer/src/main.rs

@@ -206,7 +206,9 @@ fn main() -> Result<(), Box<dyn Error>> {
                     // TODO: clk
                     bram::virtex6::add_fuzzers(&mut hammer, &backend);
                     dsp::virtex6::add_fuzzers(&mut hammer, &backend);
-                    // TODO: misc
+                    if !args.skip_misc {
+                        misc::virtex6::add_fuzzers(&mut hammer, &backend);
+                    }
                     // TODO: io
                     // TODO: pll
                     emac::virtex6::add_fuzzers(&mut hammer, &backend);
@@ -331,6 +333,9 @@ fn main() -> Result<(), Box<dyn Error>> {
                     clb::virtex5::collect_fuzzers(&mut ctx);
                     bram::virtex6::collect_fuzzers(&mut ctx);
                     dsp::virtex6::collect_fuzzers(&mut ctx);
+                    if !args.skip_misc {
+                        misc::virtex6::collect_fuzzers(&mut ctx);
+                    }
                     emac::virtex6::collect_fuzzers(&mut ctx);
                     pcie::virtex6::collect_fuzzers(&mut ctx);
                 }

prjcombine_ise_hammer/src/misc.rs

@@ -1,3 +1,4 @@
 pub mod virtex2;
 pub mod virtex4;
 pub mod virtex5;
+pub mod virtex6;

prjcombine_ise_hammer/src/misc/virtex5.rs

@@ -188,7 +188,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
     {
         let ctx = FuzzCtx::new(session, backend, "CFG", "SYSMON", TileBits::Null);
         fuzz_one_extras!(ctx, "ENABLE", "1", [], [(mode "SYSMON")], vec![
-            ExtraFeature::new(ExtraFeatureKind::HclkIoiTopCen, "HCLK_IOI_TOPCEN", "SYSMON", "ENABLE", "1"),
+            ExtraFeature::new(ExtraFeatureKind::HclkSysmonDrp, "HCLK_IOI_TOPCEN", "SYSMON", "ENABLE", "1"),
         ]);
         let ctx = FuzzCtx::new(session, backend, "CFG", "SYSMON", TileBits::Cfg);
         fuzz_inv!(ctx, "DCLK", [(mode "SYSMON")]);
@@ -334,6 +334,15 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
     fuzz_multi!(ctx, "TIMER", "", 24, [
         (no_global_opt "TIMER_USR")
     ], (global_hex "TIMER_CFG"));
+
+    let ctx = FuzzCtx::new_fake_tile(
+        session,
+        backend,
+        "REG.TESTMODE",
+        "MISC",
+        TileBits::RegPresent(Reg::Testmode),
+    );
+    fuzz_one!(ctx, "DD_OVERRIDE", "YES", [], [(global_opt "DD_OVERRIDE", "YES")]);
 }
 
 pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
@@ -570,4 +579,11 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     ctx.collect_bitvec(tile, bel, "TIMER", "");
     ctx.collect_bit(tile, bel, "TIMER_CFG", "1");
     ctx.collect_bit(tile, bel, "TIMER_USR", "1");
+
+    let tile = "REG.TESTMODE";
+    let bel = "MISC";
+    let mut diff = ctx.state.get_diff(tile, bel, "DD_OVERRIDE", "YES");
+    diff.bits.remove(&FeatureBit::new(1, 0, 0));
+    ctx.tiledb
+        .insert(tile, bel, "DD_OVERRIDE", xlat_bitvec(vec![diff]));
 }