ise_hammer: HCLK_* GLUTMASK, MCB *MR.

prjunnamed · Oct 14, 2024 · 19dd549 · 19dd549
1 parent 9f31943
commit 19dd549
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Showing 4 changed files with 88 additions and 4 deletions.
diff --git a/databases/xc6s-tiledb.json b/databases/xc6s-tiledb.json
diff --git a/docs/xilinx/spartan6/clock.rst b/docs/xilinx/spartan6/clock.rst
@@ -37,6 +37,34 @@ Bitstream — ``HCLK``
    :file: ../gen/tile-xc6s-HCLK.html
 
 
+Bitstream — ``HCLK_CLEXL``
+==========================
+
+.. raw:: html
+   :file: ../gen/tile-xc6s-HCLK_CLEXL.html
+
+
+Bitstream — ``HCLK_CLEXM``
+==========================
+
+.. raw:: html
+   :file: ../gen/tile-xc6s-HCLK_CLEXM.html
+
+
+Bitstream — ``HCLK_IOI``
+========================
+
+.. raw:: html
+   :file: ../gen/tile-xc6s-HCLK_IOI.html
+
+
+Bitstream — ``HCLK_GTP``
+========================
+
+.. raw:: html
+   :file: ../gen/tile-xc6s-HCLK_GTP.html
+
+
 Bitstream — ``HCLK_ROW``
 ========================
 

diff --git a/prjcombine_ise_hammer/src/clk/spartan6.rs b/prjcombine_ise_hammer/src/clk/spartan6.rs
@@ -4,12 +4,12 @@ use bitvec::vec::BitVec;
 use prjcombine_hammer::Session;
 use prjcombine_int::db::{BelId, Dir};
 use prjcombine_spartan6::grid::Gts;
-use prjcombine_types::TileItemKind;
+use prjcombine_types::{TileItem, TileItemKind};
 use prjcombine_xilinx_geom::ExpandedDevice;
 use unnamed_entity::EntityId;
 
 use crate::{
-    backend::IseBackend,
+    backend::{FeatureBit, IseBackend},
     diff::{xlat_bit, xlat_bit_wide, xlat_enum, xlat_enum_ocd, CollectorCtx, OcdMode},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileKV},
     fuzz::FuzzCtx,
@@ -1174,4 +1174,45 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, devdata_only: bool) {
         ctx.tiledb
             .insert(tile, bel, "PCI_CE_DELAY", xlat_enum(diffs));
     }
+    for (tile, frame, bit, target) in [
+        // used in CLEXL (incl. spine) and DSP columns; also used on PCIE sides and left GTP side
+        ("HCLK_CLEXL", 16, 0, 21),
+        ("HCLK_CLEXL", 17, 0, 22),
+        ("HCLK_CLEXL", 18, 0, 23),
+        ("HCLK_CLEXL", 19, 0, 24),
+        ("HCLK_CLEXL", 16, 1, 26),
+        ("HCLK_CLEXL", 17, 1, 27),
+        ("HCLK_CLEXL", 18, 1, 28),
+        ("HCLK_CLEXL", 19, 1, 29),
+        // used in CLEXM columns
+        ("HCLK_CLEXM", 16, 0, 21),
+        ("HCLK_CLEXM", 17, 0, 22),
+        ("HCLK_CLEXM", 18, 0, 24),
+        ("HCLK_CLEXM", 19, 0, 25),
+        ("HCLK_CLEXM", 16, 1, 27),
+        ("HCLK_CLEXM", 17, 1, 28),
+        ("HCLK_CLEXM", 18, 1, 29),
+        ("HCLK_CLEXM", 19, 1, 30),
+        // used in IOI columns
+        ("HCLK_IOI", 16, 0, 25),
+        ("HCLK_IOI", 18, 0, 23),
+        ("HCLK_IOI", 19, 0, 24),
+        ("HCLK_IOI", 16, 1, 21),
+        ("HCLK_IOI", 17, 1, 27),
+        ("HCLK_IOI", 18, 1, 28),
+        ("HCLK_IOI", 19, 1, 29),
+        // used on right GTP side
+        ("HCLK_GTP", 16, 0, 25),
+        ("HCLK_GTP", 17, 0, 22),
+        ("HCLK_GTP", 18, 0, 23),
+        ("HCLK_GTP", 19, 0, 24),
+        // BRAM columns do not have masking
+    ] {
+        ctx.tiledb.insert(
+            tile,
+            "GLUTMASK",
+            format!("FRAME{target}"),
+            TileItem::from_bit(FeatureBit::new(0, frame, bit), false),
+        )
+    }
 }
diff --git a/prjcombine_ise_hammer/src/mcb.rs b/prjcombine_ise_hammer/src/mcb.rs
@@ -1,7 +1,8 @@
 use prjcombine_hammer::Session;
+use prjcombine_types::TileItem;
 
 use crate::{
-    backend::IseBackend,
+    backend::{FeatureBit, IseBackend},
     diff::{xlat_bool, xlat_enum, CollectorCtx, Diff},
     fgen::TileBits,
     fuzz::FuzzCtx,
@@ -259,6 +260,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
     for val in ["DISABLED", "ENABLED"] {
         fuzz_one!(ctx, "MEM_PLL_DIV_EN", val, [
             (global_mutex_site "MCB"),
+            (global_mutex "DRPSDO", "NOPE"),
             (mode "MCB")
         ], [
             (global_opt "MEM_PLL_DIV_EN", val)
@@ -267,6 +269,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
     for val in ["INVERTED", "NOTINVERTED"] {
         fuzz_one!(ctx, "MEM_PLL_POL_SEL", val, [
             (global_mutex_site "MCB"),
+            (global_mutex "DRPSDO", "NOPE"),
             (mode "MCB")
         ], [
             (global_opt "MEM_PLL_POL_SEL", val)
@@ -544,4 +547,16 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     );
     ctx.collect_enum(tile, bel, "MEM_MOBILE_PA_SR", &["HALF", "FULL"]);
     ctx.collect_enum(tile, bel, "MEM_MOBILE_TC_SR", &["0", "1", "2", "3"]);
+
+    for (reg, bittile) in [("MR", 7), ("EMR1", 6), ("EMR2", 5), ("EMR3", 4)] {
+        ctx.tiledb.insert(
+            tile,
+            bel,
+            reg,
+            TileItem::from_bitvec(
+                (0..14).map(|i| FeatureBit::new(bittile, 22, 18 + i)).collect(),
+                false,
+            ),
+        );
+    }
 }