ise_hammer: xc5v IOI finish.

Cargo.toml

@@ -155,3 +155,4 @@ collapsible_else_if = "allow"
 bool_to_int_with_if = "allow"
 needless_range_loop = "allow"
 assigning_clones = "allow"
+large_enum_variant = "allow"

docs/gen_xilinx.py

@@ -342,6 +342,9 @@ def emit_dev_table_string(f, name):
         emit_misc_table("xilinx/gen/xc5v-iostd-dci-mask-term-vcc.html", "IOSTD:DCI:PMASK_TERM_VCC")
         emit_misc_table("xilinx/gen/xc5v-iostd-dci-mask-term-split.html", "IOSTD:DCI:PMASK_TERM_SPLIT", "IOSTD:DCI:NMASK_TERM_SPLIT")
 
+        with open("xilinx/gen/xc5v-iodelay-default-idelay-value.html", "w") as f:
+            emit_dev_table_bitvec(f, "IODELAY:DEFAULT_IDELAY_VALUE")
+
     if kind == "xc6v":
         emit_misc_table("xilinx/gen/xc6v-iostd-misc.html", "IOSTD:OUTPUT_MISC")
         emit_misc_table("xilinx/gen/xc6v-iostd-drive.html", "IOSTD:PDRIVE", "IOSTD:NDRIVE")

docs/xilinx/virtex5/io.rst

@@ -160,5 +160,8 @@ Bitstream
 .. raw:: html
    :file: ../gen/xc5v-iostd-lvds.html
 
+.. raw:: html
+   :file: ../gen/xc5v-iodelay-default-idelay-value.html
+
 .. raw:: html
    :file: ../gen/tile-xc5v-IO.html

docs/xilinx/virtex6/clock.rst

@@ -13,6 +13,20 @@ Clock interconnect
    :file: ../gen/tile-xc6v-HCLK.html
 
 
+``CMT_BUFG_BOT``
+================
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-CMT_BUFG_BOT.html
+
+
+``CMT_BUFG_TOP``
+================
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-CMT_BUFG_TOP.html
+
+
 ``PMVIOB``
 ==========
 

docs/xilinx/virtex6/geometry.rst

@@ -113,13 +113,12 @@ Each frame is exactly 2592 bits long and has the following structure:
 
 - bits 0-1279: interconnect rows 0 to 19 of the region, 64 bits per row
 - bits 1280-1292: ECC
-- bits 1293-1295: HCLK row
-- bits 1296-1311: unused
+- bits 1293-1311: HCLK row
 - bits 1312-2591: interconnect rows 20 to 39 of the region, 64 bits per row
 
 Every interconnect tile thus corresponds to a bitstream tile that is 28×64 to 44×64 bits. The actual interconnect tile is 26×64 bits, occupying the first 26 frames of the column. If ``INTF`` or ``INTF.DELAY`` tile is present in the tile, it occupies leftover space in frames 24 and 25.  The remaining frames, as well as unused space in frames 24-25, are used for configuring the associated primitive tile.
 
-The HCLK row has smaller bitstream tiles, 28×3 to 44×3 bits in size.
+The HCLK row has smaller bitstream tiles, 28×19 to 44×19 bits in size.
 
 The BRAM data tiles are 128×320 bits in size (covering the height of 5 interconnect rows). The area at intersection with HCLK rows is unused.
 

docs/xilinx/virtex7/geometry.rst

@@ -294,13 +294,12 @@ Each frame is exactly 3232 bits long and has the following structure:
 
 - bits 0-1599: interconnect rows 0 to 24 of the region, 64 bits per row
 - bits 1600-1612: ECC
-- bits 1613-1615: HCLK row
-- bits 1616-1631: unused
+- bits 1613-1631: HCLK row
 - bits 1632-3231: interconnect rows 25 to 49 of the region, 64 bits per row
 
 Every interconnect tile thus corresponds to a bitstream tile that is 28×64 to 42×64 bits. The actual interconnect tile is 26×64 bits, occupying the first 26 frames of the column. If ``INTF`` is present in the tile, it occupies leftover space in frames 0-3. If ``INTF.DELAY`` tile is present in the tile, it occupies leftover space in frames 0-3, as well as frames 26-27.  The remaining frames, as well as unused space in frames 0-3 and 26-27 where applicable, are used for configuring the associated primitive tile.
 
-The HCLK row has smaller bitstream tiles, 28×3 to 42×3 bits in size.
+The HCLK row has smaller bitstream tiles, 28×19 to 42×19 bits in size.
 
 The BRAM data tiles are 128×320 bits in size (covering the height of 5 interconnect rows). The area at intersection with HCLK rows is unused.
 

prjcombine_ise_hammer/src/backend.rs

@@ -510,6 +510,9 @@ impl<'a> Backend for IseBackend<'a> {
                 Key::SiteMode(site) => match v {
                     Value::None => (),
                     Value::String(s) => {
+                        if s.is_empty() {
+                            continue;
+                        }
                         insts.insert(
                             site.to_string(),
                             Instance {

prjcombine_ise_hammer/src/clb/virtex2.rs

@@ -594,7 +594,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
         ]);
     }
     if mode == Mode::Spartan3 {
-        let mut ctx = FuzzCtx::new(session, backend, "RANDOR", "RANDOR", TileBits::Main(1));
+        let mut ctx = FuzzCtx::new(session, backend, "RANDOR", "RANDOR", TileBits::Main(0, 1));
         fuzz_enum!(ctx, "ANDORMUX", ["0", "1"], [
             (mode "RESERVED_ANDOR"),
             (special TileKV::IsLeftRandor(false)),

prjcombine_ise_hammer/src/clk/virtex5.rs

@@ -6,7 +6,7 @@ use unnamed_entity::EntityId;
 use crate::{
     backend::IseBackend,
     diff::{xlat_bit, xlat_bit_wide, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
-    fgen::{BelRelation, ExtraFeature, ExtraFeatureKind, TileBits, TileRelation},
+    fgen::{BelFuzzKV, BelRelation, ExtraFeature, ExtraFeatureKind, TileBits, TileRelation},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_one, fuzz_one_extras,
 };
@@ -220,6 +220,34 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
                     (pip (bel_pin obel, format!("HCLK_O{i}")), (pin "REFCLK"))
                 ]);
             }
+            fuzz_one_extras!(ctx, "MODE", "DEFAULT_ONLY", [
+                (global_opt "LEGIDELAY", "DISABLE"),
+                (mode "")
+            ], [
+                (bel_special BelFuzzKV::AllIodelay("DEFAULT"))
+            ], vec![
+                ExtraFeature::new(
+                    ExtraFeatureKind::AllBankIoi,
+                    "IO",
+                    "IODELAY_BOTH",
+                    "IDELAYCTRL_MODE",
+                    "DEFAULT_ONLY",
+                ),
+            ]);
+            fuzz_one_extras!(ctx, "MODE", "FULL", [
+                (global_opt "LEGIDELAY", "DISABLE")
+            ], [
+                (bel_special BelFuzzKV::AllIodelay("FIXED")),
+                (mode "IDELAYCTRL")
+            ], vec![
+                ExtraFeature::new(
+                    ExtraFeatureKind::AllBankIoi,
+                    "IO",
+                    "IODELAY_BOTH",
+                    "IDELAYCTRL_MODE",
+                    "FULL",
+                ),
+            ]);
         }
     }
     {
@@ -532,9 +560,18 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     "HCLK8", "HCLK9",
                 ],
                 "NONE",
-            )
+            );
+            ctx.collect_enum_default(tile, bel, "MODE", &["FULL", "DEFAULT_ONLY"], "NONE");
         }
     }
+    {
+        let tile = "IO";
+        let bel = "IODELAY_BOTH";
+        // don't worry about it kitten
+        ctx.state
+            .get_diff(tile, bel, "IDELAYCTRL_MODE", "DEFAULT_ONLY");
+        ctx.state.get_diff(tile, bel, "IDELAYCTRL_MODE", "FULL");
+    }
     {
         let tile = "HCLK_CMT";
         let bel = "HCLK_CMT";

prjcombine_ise_hammer/src/clk/virtex6.rs

@@ -1,11 +1,13 @@
 use prjcombine_hammer::Session;
+use prjcombine_int::db::BelId;
+use unnamed_entity::EntityId;
 
 use crate::{
     backend::IseBackend,
     diff::{xlat_bit, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
     fgen::{BelRelation, TileBits},
     fuzz::FuzzCtx,
-    fuzz_enum, fuzz_one,
+    fuzz_enum, fuzz_inv, fuzz_one,
 };
 
 pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBackend<'a>) {
@@ -47,6 +49,75 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
         }
     }
 
+    for (tile, bits, base) in [
+        ("CMT_BUFG_BOT", TileBits::Main(2, 2), 0),
+        ("CMT_BUFG_TOP", TileBits::Main(0, 2), 16),
+    ] {
+        let obel_gio = BelId::from_idx(16);
+        for i in 0..16 {
+            let ctx = FuzzCtx::new(
+                session,
+                backend,
+                tile,
+                format!("BUFGCTRL{}", base + i),
+                bits.clone(),
+            );
+            fuzz_one!(ctx, "PRESENT", "1", [], [(mode "BUFGCTRL")]);
+            for pin in ["CE0", "CE1", "S0", "S1", "IGNORE0", "IGNORE1"] {
+                fuzz_inv!(ctx, pin, [(mode "BUFGCTRL")]);
+            }
+            fuzz_enum!(ctx, "PRESELECT_I0", ["FALSE", "TRUE"], [(mode "BUFGCTRL")]);
+            fuzz_enum!(ctx, "PRESELECT_I1", ["FALSE", "TRUE"], [(mode "BUFGCTRL")]);
+            fuzz_enum!(ctx, "CREATE_EDGE", ["FALSE", "TRUE"], [(mode "BUFGCTRL")]);
+            fuzz_enum!(ctx, "INIT_OUT", ["0", "1"], [(mode "BUFGCTRL")]);
+            fuzz_one!(ctx, "ENABLE.FB", "1", [], [
+                (pip (pin "O"), (pin "FB"))
+            ]);
+            // ISE bug causes pips to be reversed?
+            fuzz_one!(ctx, "TEST_I0", "1", [
+                (mutex "MUX.I0", "FB_TEST")
+            ], [
+                (pip (pin "I0_FB_TEST"), (pin "I0"))
+            ]);
+            fuzz_one!(ctx, "TEST_I1", "1", [
+                (mutex "MUX.I1", "FB_TEST")
+            ], [
+                (pip (pin "I1_FB_TEST"), (pin "I1"))
+            ]);
+            for j in 0..2 {
+                for k in 0..8 {
+                    fuzz_one!(ctx, format!("MUX.I{j}"), format!("GIO{k}"), [
+                        (mutex format!("MUX.I{j}"), format!("GIO{k}"))
+                    ], [
+                        (pip (bel_pin obel_gio, format!("GIO{k}_BUFG")), (pin format!("I{j}")))
+                    ]);
+                }
+                fuzz_one!(ctx, format!("MUX.I{j}"), "CASCI", [
+                    (mutex format!("MUX.I{j}"), "CASCI")
+                ], [
+                    (pip (pin format!("I{j}_CASCI")), (pin format!("I{j}")))
+                ]);
+                fuzz_one!(ctx, format!("MUX.I{j}"), "CKINT", [
+                    (mutex format!("MUX.I{j}"), "CKINT")
+                ], [
+                    (pip (pin format!("I{j}_CKINT")), (pin format!("I{j}")))
+                ]);
+                let obel_prev = BelId::from_idx((i + 15) % 16);
+                fuzz_one!(ctx, format!("MUX.I{j}"), "FB_PREV", [
+                    (mutex format!("MUX.I{j}"), "FB_PREV")
+                ], [
+                    (pip (bel_pin obel_prev, "FB"), (pin format!("I{j}")))
+                ]);
+                let obel_next = BelId::from_idx((i + 1) % 16);
+                fuzz_one!(ctx, format!("MUX.I{j}"), "FB_NEXT", [
+                    (mutex format!("MUX.I{j}"), "FB_NEXT")
+                ], [
+                    (pip (bel_pin obel_next, "FB"), (pin format!("I{j}")))
+                ]);
+            }
+        }
+    }
+
     {
         let ctx = FuzzCtx::new(session, backend, "PMVIOB", "PMVIOB", TileBits::MainAuto);
         fuzz_one!(ctx, "PRESENT", "1", [], [(mode "PMVIOB")]);
@@ -113,6 +184,46 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             }
         }
     }
+    for (tile, base) in [("CMT_BUFG_BOT", 0), ("CMT_BUFG_TOP", 16)] {
+        for i in 0..16 {
+            let bel = &format!("BUFGCTRL{}", base + i);
+            for pin in ["CE0", "CE1", "S0", "S1", "IGNORE0", "IGNORE1"] {
+                ctx.collect_inv(tile, bel, pin);
+            }
+            for attr in ["PRESELECT_I0", "PRESELECT_I1", "CREATE_EDGE"] {
+                ctx.collect_enum_bool(tile, bel, attr, "FALSE", "TRUE");
+            }
+            ctx.collect_enum_bool(tile, bel, "INIT_OUT", "0", "1");
+
+            // sigh. fucking. ise.
+            let mut item = xlat_bit(ctx.state.peek_diff(tile, bel, "MUX.I0", "CASCI").clone());
+            assert_eq!(item.bits.len(), 1);
+            item.bits[0].bit += 1;
+            ctx.tiledb.insert(tile, bel, "TEST_I1", item);
+            let mut item = xlat_bit(ctx.state.peek_diff(tile, bel, "MUX.I1", "CASCI").clone());
+            assert_eq!(item.bits.len(), 1);
+            item.bits[0].bit += 1;
+            ctx.tiledb.insert(tile, bel, "TEST_I0", item);
+
+            for attr in ["MUX.I0", "MUX.I1"] {
+                ctx.collect_enum_default_ocd(
+                    tile,
+                    bel,
+                    attr,
+                    &[
+                        "CASCI", "GIO0", "GIO1", "GIO2", "GIO3", "GIO4", "GIO5", "GIO6", "GIO7",
+                        "FB_PREV", "FB_NEXT", "CKINT",
+                    ],
+                    "NONE",
+                    OcdMode::Mux,
+                );
+            }
+            ctx.collect_bit(tile, bel, "ENABLE.FB", "1");
+            ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
+            ctx.state.get_diff(tile, bel, "TEST_I0", "1").assert_empty();
+            ctx.state.get_diff(tile, bel, "TEST_I1", "1").assert_empty();
+        }
+    }
 
     let tile = "PMVIOB";
     let bel = "PMVIOB";

prjcombine_ise_hammer/src/dcm/virtex.rs

@@ -23,7 +23,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
     for tile in [
         "DLL.BOT", "DLL.TOP", "DLLP.BOT", "DLLP.TOP", "DLLS.BOT", "DLLS.TOP",
     ] {
-        let Some(ctx) = FuzzCtx::try_new(session, backend, tile, "DLL", TileBits::Main(1)) else {
+        let Some(ctx) = FuzzCtx::try_new(session, backend, tile, "DLL", TileBits::Main(0, 1)) else {
             continue;
         };
         fuzz_one_extras!(ctx, "PRESENT", "1", [