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ise_hammer: 4v mgt
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@wanda-phi
wanda-phi committed Jul 17, 2024
1 parent 9af6c0b commit 4508111
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Showing 13 changed files with 983 additions and 50 deletions.
2 changes: 1 addition & 1 deletion databases/xc4v-tiledb.json
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7 changes: 7 additions & 0 deletions docs/xilinx/virtex4/clock.rst
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Expand Up @@ -150,3 +150,10 @@ IO clock nodes

.. raw:: html
:file: ../gen/tile-xc4v-HCLK_DCM.html


``HCLK_MGT``
============

.. raw:: html
:file: ../gen/tile-xc4v-HCLK_MGT.html
13 changes: 13 additions & 0 deletions docs/xilinx/virtex4/gt.rst
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@@ -0,0 +1,13 @@
.. _virtex4-gt:

Multi-gigabit transceivers
##########################

.. todo:: document


Bitstream
=========

.. raw:: html
:file: ../gen/tile-xc4v-MGT.html
1 change: 1 addition & 0 deletions docs/xilinx/virtex4/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -17,3 +17,4 @@ Virtex 4
ccm
config
sysmon
gt
29 changes: 19 additions & 10 deletions prjcombine_ise_hammer/src/clk/virtex4.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -121,11 +121,11 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
let obel = BelId::from_idx(0);
fuzz_one!(ctx, hclk, "1", [
(global_mutex "BUFGCTRL_OUT", "USE"),
(related TileRelation::ClkHrow,
(related TileRelation::ClkHrow(0),
(tile_mutex "MODE", "USE")),
(related TileRelation::ClkHrow,
(related TileRelation::ClkHrow(0),
(pip (bel_pin obel, "GCLK0"), (bel_pin obel, hclk_l))),
(related TileRelation::ClkHrow,
(related TileRelation::ClkHrow(0),
(pip (bel_pin obel, "GCLK0"), (bel_pin obel, hclk_r)))
], [
(pip (pin hclk_i), (pin hclk_o))
Expand Down Expand Up @@ -206,11 +206,11 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
let obel = BelId::from_idx(0);
fuzz_one!(ctx, hclk, "1", [
(global_mutex "BUFGCTRL_OUT", "USE"),
(related TileRelation::ClkHrow,
(related TileRelation::ClkHrow(0),
(tile_mutex "MODE", "USE")),
(related TileRelation::ClkHrow,
(related TileRelation::ClkHrow(0),
(pip (bel_pin obel, "GCLK0"), (bel_pin obel, hclk_l))),
(related TileRelation::ClkHrow,
(related TileRelation::ClkHrow(0),
(pip (bel_pin obel, "GCLK0"), (bel_pin obel, hclk_r)))
], [
(pip (pin hclk_i), (pin hclk_o))
Expand Down Expand Up @@ -374,9 +374,9 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
(global_mutex "HCLK_DCM", "TEST"),
(tile_mutex "HCLK_DCM", format!("HCLK_O_{ud}{i}")),
(global_mutex "BUFGCTRL_OUT", "USE"),
(related TileRelation::ClkHrow,
(related TileRelation::ClkHrow(0),
(tile_mutex "MODE", "USE")),
(related TileRelation::ClkHrow,
(related TileRelation::ClkHrow(0),
(pip (bel_pin obel, "GCLK0"), (bel_pin obel, format!("HCLK_L{i}")))),
(special TileKV::HclkHasDcm(dir))
], [
Expand Down Expand Up @@ -421,12 +421,13 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
None,
),
"HCLK_MGT_REPEATER",
"CLK_MGT_REPEATER",
format!("MGT{idx}", idx = i % 2),
"HCLK_MGT_REPEATER",
format!("BUF.MGT{idx}.DCM", idx = i % 2),
"1",
));
}
fuzz_one_extras!(ctx, format!("MGT_O_{ud}{i}"), "1", [
(global_mutex "MGT_OUT", "USE"),
(global_mutex "HCLK_DCM", "TEST"),
(tile_mutex "HCLK_DCM", format!("MGT_O_{ud}{i}"))
], [
Expand Down Expand Up @@ -783,4 +784,12 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
}
}
}
if edev.col_lgt.is_some() && !edev.grids[edev.grid_master].cols_vbrk.is_empty() {
let tile = "HCLK_MGT_REPEATER";
let bel = "HCLK_MGT_REPEATER";
let item = ctx.extract_bit(tile, bel, "BUF.MGT0.DCM", "1");
ctx.tiledb.insert(tile, bel, "BUF.MGT0", item);
let item = ctx.extract_bit(tile, bel, "BUF.MGT1.DCM", "1");
ctx.tiledb.insert(tile, bel, "BUF.MGT1", item);
}
}
92 changes: 63 additions & 29 deletions prjcombine_ise_hammer/src/fgen.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -34,11 +34,12 @@ pub enum TileRelation {
IobBrefclkClkBT,
ClkIob(Dir),
ClkDcm,
ClkHrow,
ClkHrow(usize),
Rclk,
Ioclk(Dir),
Cfg,
HclkDcm,
Mgt(Dir),
}

#[derive(Debug, Copy, Clone, Eq, PartialEq)]
Expand Down Expand Up @@ -172,14 +173,15 @@ fn resolve_tile_relation(
| prjcombine_virtex4::grid::GridKind::Virtex7 => unreachable!(),
}
}
TileRelation::ClkHrow => match backend.edev {
TileRelation::ClkHrow(delta) => match backend.edev {
ExpandedDevice::Xc4k(_) => todo!(),
ExpandedDevice::Xc5200(_) => todo!(),
ExpandedDevice::Virtex(_) => todo!(),
ExpandedDevice::Virtex2(_) => todo!(),
ExpandedDevice::Spartan6(_) => todo!(),
ExpandedDevice::Virtex4(edev) => {
loc.1 = edev.col_clk;
loc.2 += delta;
let Some((layer, _)) = backend.egrid.find_node_loc(loc.0, (loc.1, loc.2), |node| {
backend
.egrid
Expand Down Expand Up @@ -245,6 +247,42 @@ fn resolve_tile_relation(
ExpandedDevice::Ultrascale(_) => todo!(),
ExpandedDevice::Versal(_) => todo!(),
},
TileRelation::Mgt(dir) => {
let ExpandedDevice::Virtex4(edev) = backend.edev else {
unreachable!()
};
match edev.kind {
prjcombine_virtex4::grid::GridKind::Virtex4 => {
match dir {
Dir::S => {
if loc.2.to_idx() == 0 {
return None;
}
loc.2 -= 32
}
Dir::N => {
loc.2 += 32;
if loc.2.to_idx() >= edev.grids[loc.0].rows().len() {
return None;
}
}
_ => unreachable!(),
}
let Some((layer, _)) =
backend.egrid.find_node_loc(loc.0, (loc.1, loc.2), |node| {
backend.egrid.db.nodes.key(node.kind) == "MGT"
})
else {
unreachable!()
};
loc.3 = layer;
Some(loc)
}
prjcombine_virtex4::grid::GridKind::Virtex5 => todo!(),
prjcombine_virtex4::grid::GridKind::Virtex6 => todo!(),
prjcombine_virtex4::grid::GridKind::Virtex7 => todo!(),
}
}
}
}

Expand Down Expand Up @@ -2100,10 +2138,7 @@ impl TileBits {
]
}
TileBits::RegPresent(reg) => {
vec![
BitTile::Reg(die, reg),
BitTile::RegPresent(die, reg),
]
vec![BitTile::Reg(die, reg), BitTile::RegPresent(die, reg)]
}
TileBits::Pcie => {
let ExpandedDevice::Virtex4(edev) = backend.edev else {
Expand Down Expand Up @@ -2147,12 +2182,12 @@ pub enum ExtraFeatureKind {
HclkDcm(Dir),
HclkCcm(Dir),
MgtRepeater(Dir, Option<Dir>),
MgtRepeaterMgt(usize),
BufpllPll(Dir, &'static str),
Reg(Reg),
HclkSysmonDrp,
Hclk(usize, usize),
HclkIoiCenter(&'static str),
HclkBramMgtPrev,
PcieHclk,
PcieHclkPair,
Pcie3HclkPair,
}
Expand Down Expand Up @@ -2343,6 +2378,24 @@ impl ExtraFeatureKind {
}
res
}
ExtraFeatureKind::MgtRepeaterMgt(delta) => {
let ExpandedDevice::Virtex4(edev) = backend.edev else {
unreachable!()
};
let row = loc.2 + delta;
let mut res = vec![];
let is_l = loc.1 < edev.col_cfg;
for &col in &edev.grids[edev.grid_master].cols_vbrk {
if (col < edev.col_cfg) == is_l {
res.push(vec![edev.btile_hclk(
DieId::from_idx(0),
if is_l { col } else { col - 1 },
row,
)]);
}
}
res
}
ExtraFeatureKind::BufpllPll(dir, kind) => {
let ExpandedDevice::Spartan6(edev) = backend.edev else {
unreachable!()
Expand Down Expand Up @@ -2380,20 +2433,11 @@ impl ExtraFeatureKind {
.ids()
.map(|die| vec![BitTile::Reg(die, reg)])
.collect(),
ExtraFeatureKind::HclkSysmonDrp => {
ExtraFeatureKind::Hclk(dx, dy) => {
let ExpandedDevice::Virtex4(edev) = backend.edev else {
unreachable!()
};
match edev.kind {
prjcombine_virtex4::grid::GridKind::Virtex4 => todo!(),
prjcombine_virtex4::grid::GridKind::Virtex5 => {
vec![vec![edev.btile_hclk(loc.0, loc.1, loc.2 + 20)]]
}
prjcombine_virtex4::grid::GridKind::Virtex6 => {
vec![vec![edev.btile_hclk(loc.0, loc.1, loc.2 + 20)]]
}
prjcombine_virtex4::grid::GridKind::Virtex7 => todo!(),
}
vec![vec![edev.btile_hclk(loc.0, loc.1 + dx, loc.2 + dy)]]
}
ExtraFeatureKind::HclkIoiCenter(kind) => {
let ExpandedDevice::Virtex4(edev) = backend.edev else {
Expand Down Expand Up @@ -2431,16 +2475,6 @@ impl ExtraFeatureKind {
None => vec![],
}
}
ExtraFeatureKind::PcieHclk => {
let ExpandedDevice::Virtex4(edev) = backend.edev else {
unreachable!()
};
vec![vec![edev.btile_hclk(
loc.0,
loc.1 + 3,
loc.2 + edev.grids[loc.0].rows_per_reg() / 2,
)]]
}
ExtraFeatureKind::PcieHclkPair => {
let ExpandedDevice::Virtex4(edev) = backend.edev else {
unreachable!()
Expand Down
1 change: 1 addition & 0 deletions prjcombine_ise_hammer/src/gt.rs
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Original file line number Diff line number Diff line change
@@ -1,2 +1,3 @@
pub mod virtex2p;
pub mod virtex2px;
pub mod virtex4;
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