ise_hammer: xc4000.

Cargo.toml

@@ -10,7 +10,7 @@ members = [
 	"prjcombine_lattice_dump",
 	"prjcombine_lattice_rawdump",
 	"prjcombine_int",
-	"prjcombine_xc4k",
+	"prjcombine_xc4000",
 	"prjcombine_xc5200",
 	"prjcombine_virtex",
 	"prjcombine_virtex2",
@@ -21,7 +21,7 @@ members = [
 	"prjcombine_rdgrid",
 	"prjcombine_rdintb",
 	"prjcombine_rdverify",
-	"prjcombine_xc4k_rdverify",
+	"prjcombine_xc4000_rdverify",
 	"prjcombine_xc5200_rdverify",
 	"prjcombine_virtex_rdverify",
 	"prjcombine_virtex2_rdverify",
@@ -32,7 +32,7 @@ members = [
 	"prjcombine_virtex7_rdverify",
 	"prjcombine_ultrascale_rdverify",
 	"prjcombine_versal_rdverify",
-	"prjcombine_xc4k_rd2db",
+	"prjcombine_xc4000_rd2db",
 	"prjcombine_xc5200_rd2db",
 	"prjcombine_virtex_rd2db",
 	"prjcombine_virtex2_rd2db",
@@ -74,9 +74,9 @@ prjcombine_int = { path = "prjcombine_int" }
 prjcombine_rdgrid = { path = "prjcombine_rdgrid" }
 prjcombine_rdintb = { path = "prjcombine_rdintb" }
 prjcombine_rdverify = { path = "prjcombine_rdverify" }
-prjcombine_xc4k = { path = "prjcombine_xc4k" }
-prjcombine_xc4k_rdverify = { path = "prjcombine_xc4k_rdverify" }
-prjcombine_xc4k_rd2db = { path = "prjcombine_xc4k_rd2db" }
+prjcombine_xc4000 = { path = "prjcombine_xc4000" }
+prjcombine_xc4000_rdverify = { path = "prjcombine_xc4000_rdverify" }
+prjcombine_xc4000_rd2db = { path = "prjcombine_xc4000_rd2db" }
 prjcombine_xc5200 = { path = "prjcombine_xc5200" }
 prjcombine_xc5200_rdverify = { path = "prjcombine_xc5200_rdverify" }
 prjcombine_xc5200_rd2db = { path = "prjcombine_xc5200_rd2db" }
@@ -157,3 +157,4 @@ bool_to_int_with_if = "allow"
 needless_range_loop = "allow"
 assigning_clones = "allow"
 large_enum_variant = "allow"
+nonminimal_bool = "allow"

docs/gen_xilinx.py

@@ -1,6 +1,9 @@
 import json
 
-for kind in ["xc5k", "xcv", "xc2v", "xc3s", "xcexf", "xc6s", "xc4v", "xc5v", "xc6v", "xc7v"]:
+for kind in [
+    "xc4ke", "xc4kex", "xc4kxla", "xc4kxv", "xcsxl", "xc5k", "xcv",
+    "xc2v", "xc3s", "xcexf", "xc6s", "xc4v", "xc5v", "xc6v", "xc7v"
+]:
     with open(f"../databases/{kind}-tiledb.json") as dbf:
         db = json.load(dbf)
 

docs/xilinx/index.rst

@@ -5,6 +5,11 @@ Xilinx FPGAs
    :maxdepth: 2
    :caption: Contents:
 
+   xc4000e/index
+   xc4000ex/index
+   xc4000xla/index
+   xc4000xv/index
+   spartanxl/index
    xc5200/index
    virtex/index
    virtex2/index

docs/xilinx/spartanxl/clb.rst

@@ -0,0 +1,65 @@
+Configurable Logic Block
+########################
+
+
+``CLB``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.html
+
+
+``CLB.L``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.L.html
+
+
+``CLB.R``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.R.html
+
+
+``CLB.B``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.B.html
+
+
+``CLB.LB``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.LB.html
+
+
+``CLB.RB``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.RB.html
+
+
+``CLB.T``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.T.html
+
+
+``CLB.LT``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.LT.html
+
+
+``CLB.RT``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.RT.html

docs/xilinx/spartanxl/corner.rst

@@ -0,0 +1,30 @@
+Corners
+#######
+
+
+``CNR.BL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CNR.BL.html
+
+
+``CNR.TL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CNR.TL.html
+
+
+``CNR.BR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CNR.BR.html
+
+
+``CNR.TR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CNR.TR.html

docs/xilinx/spartanxl/index.rst

@@ -0,0 +1,14 @@
+Spartan XL
+##########
+
+.. todo:: intro document, bitstream format, other tiles, jtag, ...
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   clb
+   io
+   corner
+   splitter
+

docs/xilinx/spartanxl/io.rst

@@ -0,0 +1,114 @@
+Input/Output
+############
+
+
+``IO.L``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.L.html
+
+
+``IO.L.T``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.L.T.html
+
+
+``IO.LS``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.LS.html
+
+
+``IO.LS.B``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.LS.B.html
+
+
+``IO.R``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.R.html
+
+
+``IO.R.T``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.R.T.html
+
+
+``IO.RS``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.RS.html
+
+
+``IO.RS.B``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.RS.B.html
+
+
+``IO.B``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.B.html
+
+
+``IO.B.R``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.B.R.html
+
+
+``IO.BS``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.BS.html
+
+
+``IO.BS.L``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.BS.L.html
+
+
+``IO.T``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.T.html
+
+
+``IO.T.R``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.T.R.html
+
+
+``IO.TS``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.TS.html
+
+
+``IO.TS.L``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.TS.L.html

docs/xilinx/spartanxl/splitter.rst

@@ -0,0 +1,51 @@
+Splitters
+#########
+
+
+``LLH.CLB``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLH.CLB.html
+
+
+``LLH.CLB.B``
+=============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLH.CLB.B.html
+
+
+``LLH.IO.B``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLH.IO.B.html
+
+
+``LLH.IO.T``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLH.IO.T.html
+
+
+``LLV.CLB``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLV.CLB.html
+
+
+``LLV.IO.L``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLV.IO.L.html
+
+
+``LLV.IO.R``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLV.IO.R.html