xact_hammer: add.

prjunnamed · Dec 1, 2024 · 5cdc6ed · 5cdc6ed
1 parent cdaf16a
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diff --git a/Cargo.toml b/Cargo.toml
@@ -61,8 +61,9 @@ members = [
 	"prjcombine_xact_naming",
 	"prjcombine_xc2000_xact",
 	"prjcombine_xact_data",
-	"prjcombine_xact_dump",
 	"prjcombine_xact_geom",
+	"prjcombine_xact_dump",
+	"prjcombine_xact_hammer",
 	"prjcombine_vm6",
 	"prjcombine_xilinx_cpld",
 	"prjcombine_xilinx_recpld",

diff --git a/README.md b/README.md
@@ -26,12 +26,12 @@ See https://prjunnamed.github.io/prjcombine/
 - Xilinx Coolrunner 2 CPLDs: phase 4 in progress
 - Xilinx FPGAs:
 
-  - XC2000, XC2000L: phase 1 complete
-  - XC3000, XC3100: phase 1 complete
-  - XC3000A, XC3100A, XC3000L, XC3100L: phase 1 complete
-  - XC4000, XC4000D: phase 1 complete
-  - XC4000A: phase 1 complete
-  - XC4000H: phase 1 complete
+  - XC2000, XC2000L: phase 2 complete
+  - XC3000, XC3100: phase 2 complete
+  - XC3000A, XC3100A, XC3000L, XC3100L: phase 2 complete
+  - XC4000, XC4000D: phase 2 complete
+  - XC4000A: phase 2 complete
+  - XC4000H: phase 2 complete
   - XC4000E, XC4000L, Spartan: phase 2 complete
   - XC4000EX, XC4000XL: phase 2 complete
   - XC4000XLA: phase 2 complete

diff --git a/databases/xc2k-tiledb.json b/databases/xc2k-tiledb.json
diff --git a/databases/xc3k-tiledb.json b/databases/xc3k-tiledb.json
diff --git a/databases/xc3ka-tiledb.json b/databases/xc3ka-tiledb.json
diff --git a/databases/xc4k-tiledb.json b/databases/xc4k-tiledb.json
diff --git a/databases/xc4ka-tiledb.json b/databases/xc4ka-tiledb.json
diff --git a/databases/xc4ke-tiledb.json b/databases/xc4ke-tiledb.json
diff --git a/databases/xc4kex-tiledb.json b/databases/xc4kex-tiledb.json
diff --git a/databases/xc4kh-tiledb.json b/databases/xc4kh-tiledb.json
diff --git a/databases/xc4kxla-tiledb.json b/databases/xc4kxla-tiledb.json
diff --git a/databases/xc5k-tiledb.json b/databases/xc5k-tiledb.json
diff --git a/databases/xc5kx-tiledb.json b/databases/xc5kx-tiledb.json
diff --git a/databases/xcsxl-tiledb.json b/databases/xcsxl-tiledb.json
diff --git a/docs/gen_xilinx.py b/docs/gen_xilinx.py
@@ -1,8 +1,14 @@
 import json
 
 for kind in [
-    "xc4ke", "xc4kex", "xc4kxla", "xc4kxv", "xcsxl", "xc5k", "xcv",
-    "xc2v", "xc3s", "xcexf", "xc6s", "xc4v", "xc5v", "xc6v", "xc7v"
+    "xc2k",
+    "xc3k", "xc3ka",
+    "xc4k", "xc4ka","xc4kh", "xc4ke", "xc4kex", "xc4kxla", "xc4kxv", "xcsxl",
+    "xc5k",
+    "xcv",
+    "xc2v", "xc3s", "xcexf",
+    "xc6s",
+    "xc4v", "xc5v", "xc6v", "xc7v"
 ]:
     with open(f"../databases/{kind}-tiledb.json") as dbf:
         db = json.load(dbf)

diff --git a/docs/xilinx/index.rst b/docs/xilinx/index.rst
@@ -5,6 +5,12 @@ Xilinx FPGAs
    :maxdepth: 2
    :caption: Contents:
 
+   xc2000/index
+   xc3000/index
+   xc3000a/index
+   xc4000/index
+   xc4000a/index
+   xc4000h/index
    xc4000e/index
    xc4000ex/index
    xc4000xla/index

diff --git a/docs/xilinx/xc2000/bidi.rst b/docs/xilinx/xc2000/bidi.rst
@@ -0,0 +1,44 @@
+Bidi buffers
+############
+
+
+``BIDIH``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIH.html
+
+
+``BIDIH.B``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIH.B.html
+
+
+``BIDIH.T``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIH.T.html
+
+
+``BIDIV``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIV.html
+
+
+``BIDIV.L``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIV.L.html
+
+
+``BIDIV.R``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIV.R.html
diff --git a/docs/xilinx/xc2000/clb.rst b/docs/xilinx/xc2000/clb.rst
@@ -0,0 +1,93 @@
+Configurable Logic Block
+########################
+
+
+``CLB``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.html
+
+
+``CLB.L``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.L.html
+
+
+``CLB.R``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.R.html
+
+
+``CLB.ML``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.ML.html
+
+
+``CLB.MR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.MR.html
+
+
+``CLB.B``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.B.html
+
+
+``CLB.BR1``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.BR1.html
+
+
+``CLB.BL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.BL.html
+
+
+``CLB.BR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.BR.html
+
+
+``CLB.T``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.T.html
+
+
+``CLB.TR1``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.TR1.html
+
+
+``CLB.TL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.TL.html
+
+
+``CLB.TR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.TR.html
diff --git a/docs/xilinx/xc2000/index.rst b/docs/xilinx/xc2000/index.rst
@@ -0,0 +1,11 @@
+XC2000
+######
+
+.. todo:: intro document, bitstream format, ...
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   clb
+   bidi