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prjunnamed · Sep 16, 2024 · 784f0cd · 784f0cd
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diff --git a/_sources/xilinx/virtex5/io.rst.txt b/_sources/xilinx/virtex5/io.rst.txt
@@ -160,5 +160,8 @@ Bitstream
 .. raw:: html
    :file: ../gen/xc5v-iostd-lvds.html
 
+.. raw:: html
+   :file: ../gen/xc5v-iodelay-default-idelay-value.html
+
 .. raw:: html
    :file: ../gen/tile-xc5v-IO.html
diff --git a/_sources/xilinx/virtex6/clock.rst.txt b/_sources/xilinx/virtex6/clock.rst.txt
@@ -13,6 +13,20 @@ Clock interconnect
    :file: ../gen/tile-xc6v-HCLK.html
 
 
+``CMT_BUFG_BOT``
+================
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-CMT_BUFG_BOT.html
+
+
+``CMT_BUFG_TOP``
+================
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-CMT_BUFG_TOP.html
+
+
 ``PMVIOB``
 ==========
 

diff --git a/_sources/xilinx/virtex6/geometry.rst.txt b/_sources/xilinx/virtex6/geometry.rst.txt
@@ -113,13 +113,12 @@ Each frame is exactly 2592 bits long and has the following structure:
 
 - bits 0-1279: interconnect rows 0 to 19 of the region, 64 bits per row
 - bits 1280-1292: ECC
-- bits 1293-1295: HCLK row
-- bits 1296-1311: unused
+- bits 1293-1311: HCLK row
 - bits 1312-2591: interconnect rows 20 to 39 of the region, 64 bits per row
 
 Every interconnect tile thus corresponds to a bitstream tile that is 28×64 to 44×64 bits. The actual interconnect tile is 26×64 bits, occupying the first 26 frames of the column. If ``INTF`` or ``INTF.DELAY`` tile is present in the tile, it occupies leftover space in frames 24 and 25.  The remaining frames, as well as unused space in frames 24-25, are used for configuring the associated primitive tile.
 
-The HCLK row has smaller bitstream tiles, 28×3 to 44×3 bits in size.
+The HCLK row has smaller bitstream tiles, 28×19 to 44×19 bits in size.
 
 The BRAM data tiles are 128×320 bits in size (covering the height of 5 interconnect rows). The area at intersection with HCLK rows is unused.
 

diff --git a/_sources/xilinx/virtex7/geometry.rst.txt b/_sources/xilinx/virtex7/geometry.rst.txt
@@ -294,13 +294,12 @@ Each frame is exactly 3232 bits long and has the following structure:
 
 - bits 0-1599: interconnect rows 0 to 24 of the region, 64 bits per row
 - bits 1600-1612: ECC
-- bits 1613-1615: HCLK row
-- bits 1616-1631: unused
+- bits 1613-1631: HCLK row
 - bits 1632-3231: interconnect rows 25 to 49 of the region, 64 bits per row
 
 Every interconnect tile thus corresponds to a bitstream tile that is 28×64 to 42×64 bits. The actual interconnect tile is 26×64 bits, occupying the first 26 frames of the column. If ``INTF`` is present in the tile, it occupies leftover space in frames 0-3. If ``INTF.DELAY`` tile is present in the tile, it occupies leftover space in frames 0-3, as well as frames 26-27.  The remaining frames, as well as unused space in frames 0-3 and 26-27 where applicable, are used for configuring the associated primitive tile.
 
-The HCLK row has smaller bitstream tiles, 28×3 to 42×3 bits in size.
+The HCLK row has smaller bitstream tiles, 28×19 to 42×19 bits in size.
 
 The BRAM data tiles are 128×320 bits in size (covering the height of 5 interconnect rows). The area at intersection with HCLK rows is unused.
 

diff --git a/searchindex.js b/searchindex.js
diff --git a/xilinx/virtex4/io.html b/xilinx/virtex4/io.html
diff --git a/xilinx/virtex5/clock.html b/xilinx/virtex5/clock.html
diff --git a/xilinx/virtex5/io.html b/xilinx/virtex5/io.html
diff --git a/xilinx/virtex6/clock.html b/xilinx/virtex6/clock.html
diff --git a/xilinx/virtex6/geometry.html b/xilinx/virtex6/geometry.html
@@ -209,12 +209,11 @@ <h2>Bitstream geometry<a class="headerlink" href="#bitstream-geometry" title="Li
 <ul class="simple">
 <li><p>bits 0-1279: interconnect rows 0 to 19 of the region, 64 bits per row</p></li>
 <li><p>bits 1280-1292: ECC</p></li>
-<li><p>bits 1293-1295: HCLK row</p></li>
-<li><p>bits 1296-1311: unused</p></li>
+<li><p>bits 1293-1311: HCLK row</p></li>
 <li><p>bits 1312-2591: interconnect rows 20 to 39 of the region, 64 bits per row</p></li>
 </ul>
 <p>Every interconnect tile thus corresponds to a bitstream tile that is 28×64 to 44×64 bits. The actual interconnect tile is 26×64 bits, occupying the first 26 frames of the column. If <code class="docutils literal notranslate"><span class="pre">INTF</span></code> or <code class="docutils literal notranslate"><span class="pre">INTF.DELAY</span></code> tile is present in the tile, it occupies leftover space in frames 24 and 25.  The remaining frames, as well as unused space in frames 24-25, are used for configuring the associated primitive tile.</p>
-<p>The HCLK row has smaller bitstream tiles, 28×3 to 44×3 bits in size.</p>
+<p>The HCLK row has smaller bitstream tiles, 28×19 to 44×19 bits in size.</p>
 <p>The BRAM data tiles are 128×320 bits in size (covering the height of 5 interconnect rows). The area at intersection with HCLK rows is unused.</p>
 <section id="ecc">
 <h3>ECC<a class="headerlink" href="#ecc" title="Link to this heading"></a></h3>

diff --git a/xilinx/virtex6/index.html b/xilinx/virtex6/index.html
@@ -147,6 +147,8 @@ <h1>Virtex 6<a class="headerlink" href="#virtex-6" title="Link to this heading">
 </li>
 <li class="toctree-l1"><a class="reference internal" href="clock.html">Clock interconnect</a><ul>
 <li class="toctree-l2"><a class="reference internal" href="clock.html#hclk"><code class="docutils literal notranslate"><span class="pre">HCLK</span></code></a></li>
+<li class="toctree-l2"><a class="reference internal" href="clock.html#cmt-bufg-bot"><code class="docutils literal notranslate"><span class="pre">CMT_BUFG_BOT</span></code></a></li>
+<li class="toctree-l2"><a class="reference internal" href="clock.html#cmt-bufg-top"><code class="docutils literal notranslate"><span class="pre">CMT_BUFG_TOP</span></code></a></li>
 <li class="toctree-l2"><a class="reference internal" href="clock.html#pmviob"><code class="docutils literal notranslate"><span class="pre">PMVIOB</span></code></a></li>
 </ul>
 </li>

diff --git a/xilinx/virtex7/geometry.html b/xilinx/virtex7/geometry.html
@@ -358,12 +358,11 @@ <h2>Bitstream geometry<a class="headerlink" href="#bitstream-geometry" title="Li
 <ul class="simple">
 <li><p>bits 0-1599: interconnect rows 0 to 24 of the region, 64 bits per row</p></li>
 <li><p>bits 1600-1612: ECC</p></li>
-<li><p>bits 1613-1615: HCLK row</p></li>
-<li><p>bits 1616-1631: unused</p></li>
+<li><p>bits 1613-1631: HCLK row</p></li>
 <li><p>bits 1632-3231: interconnect rows 25 to 49 of the region, 64 bits per row</p></li>
 </ul>
 <p>Every interconnect tile thus corresponds to a bitstream tile that is 28×64 to 42×64 bits. The actual interconnect tile is 26×64 bits, occupying the first 26 frames of the column. If <code class="docutils literal notranslate"><span class="pre">INTF</span></code> is present in the tile, it occupies leftover space in frames 0-3. If <code class="docutils literal notranslate"><span class="pre">INTF.DELAY</span></code> tile is present in the tile, it occupies leftover space in frames 0-3, as well as frames 26-27.  The remaining frames, as well as unused space in frames 0-3 and 26-27 where applicable, are used for configuring the associated primitive tile.</p>
-<p>The HCLK row has smaller bitstream tiles, 28×3 to 42×3 bits in size.</p>
+<p>The HCLK row has smaller bitstream tiles, 28×19 to 42×19 bits in size.</p>
 <p>The BRAM data tiles are 128×320 bits in size (covering the height of 5 interconnect rows). The area at intersection with HCLK rows is unused.</p>
 <section id="ecc">
 <h3>ECC<a class="headerlink" href="#ecc" title="Link to this heading"></a></h3>