docs: start documenting Spartan 3.

docs/xilinx/spartan3/clb.rst

@@ -1,16 +1,29 @@
+.. _spartan3-clb:
+
 Configurable Logic Block — Spartan 3, Virtex 4
 ##############################################
 
+.. todo:: document
+
+
+Bitstream
+=========
 
-Bitstream — Spartan 3
-=====================
+The data for a CLB is located in the same bitstream tile as the associated ``INT.CLB`` or ``INT`` tile.
+
+Spartan 3
+---------
+
+This tile is used on Spartan 3 devices (all kinds).
 
 .. raw:: html
    :file: ../gen-xilinx-tile-xc3s-CLB.html
 
 
-Bitstream — Virtex 4
-====================
+Virtex 4
+--------
+
+This tile is used on Virtex 4 devices.
 
 .. raw:: html
    :file: ../gen-xilinx-tile-xc4v-CLB.html

docs/xilinx/spartan3/clock.rst

@@ -1,41 +1,126 @@
+.. _spartan3-clock:
+
 Clock interconnect
 ==================
 
+.. todo:: document
+
+
 Clock source — spine bottom and top
------------------------------------
+===================================
+
+.. todo:: document
+
+
+Bitstream — bottom tiles
+------------------------
+
+The ``CLKB.*`` tiles use two bitstream tiles:
 
-Bitstream — Spartan 3 bottom
-++++++++++++++++++++++++++++
+- tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the bottom interconnect row
+- tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the low special area (used for bottom ``IOB`` tiles and clock rows in normal columns)
+
+On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the ``LLH.CLKB.S3A`` tile.
+
+
+``CLKB.S3``
++++++++++++
+
+This tile is used on Spartan 3.
 
 .. raw:: html
    :file: ../gen-xilinx-tile-xc3s-CLKB.S3.html
 
-Bitstream — Spartan 3 top
-+++++++++++++++++++++++++
 
-.. raw:: html
-   :file: ../gen-xilinx-tile-xc3s-CLKT.S3.html
+``CLKB.S3E``
+++++++++++++
 
-Bitstream — Spartan 3E bottom
-+++++++++++++++++++++++++++++
+This tile is used on Spartan 3E.
 
 .. raw:: html
    :file: ../gen-xilinx-tile-xc3s-CLKB.S3E.html
 
-Bitstream — Spartan 3E top
-++++++++++++++++++++++++++
 
-.. raw:: html
-   :file: ../gen-xilinx-tile-xc3s-CLKT.S3E.html
+``CLKB.S3A``
+++++++++++++
 
-Bitstream — Spartan 3A bottom
-+++++++++++++++++++++++++++++
+This tile is used on Spartan 3A and 3A DSP.
 
 .. raw:: html
    :file: ../gen-xilinx-tile-xc3s-CLKB.S3A.html
 
-Bitstream — Spartan 3A top
-++++++++++++++++++++++++++
+
+Bitstream — top tiles
+---------------------
+
+The ``CLKT.*`` tiles use two bitstream tiles:
+
+- tile 0: 1×64 (Spartan 3, 3E) or 2×64 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the top interconnect row
+- tile 1: 1×16 (Spartan 3, 3E) or 2×16 (Spartan 3A) tile located in the primary clock spine column, in the bits corresponding to the high special area (used for top ``IOB`` tiles and clock rows in normal columns)
+
+On Spartan 3A devices that have long line splitters, bitstream tile 0 is shared with the ``LLH.CLKT.S3A`` tile.
+
+
+``CLKT.S3``
++++++++++++
+
+This tile is used on Spartan 3.
 
 .. raw:: html
-   :file: ../gen-xilinx-tile-xc3s-CLKT.S3A.html
+   :file: ../gen-xilinx-tile-xc3s-CLKT.S3.html
+
+
+``CLKT.S3E``
+++++++++++++
+
+This tile is used on Spartan 3E.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-CLKT.S3E.html
+
+
+``CLKT.S3A``
+++++++++++++
+
+This tile is used on Spartan 3A and 3A DSP.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-CLKT.S3A.html
+
+
+Clock source — left and right
+=============================
+
+.. todo:: document
+
+
+The ``CLKC`` clock center tile
+==============================
+
+The ``CLKC`` tile is located in the center of the FPGA (intersection of primary vertical and horizontal clock spines) of all devices except ``xc3s50a``. It has permanent buffers forwarding the clock signals from ``CLKB`` and ``CLKT`` to ``GCLKVM``. It has no configuration.
+
+.. todo:: describe exact forwarding
+
+
+The ``GCLKVM`` secondary clock center tiles
+===========================================
+
+The ``GCLKVM`` tiles are located on the intersection of secondary vertical clock spines and the horizontal clock spine.
+
+The Spartan 3 version has permanent buffers forwarding the clock signals from ``CLKC`` to ``GCLKVC`` tiles. It has no configuration.
+
+The Spartan 3E and 3A versions multiplex clock signals from ``CLK[LR]`` and ``CLKC`` tiles.
+
+.. todo:: document Spartan 3E/3A version
+
+
+The ``GCLKVC`` clock spine distribution tiles
+=============================================
+
+.. todo:: document
+
+
+The ``GCLKH`` clock row distribution tiles
+==========================================
+
+.. todo:: document

docs/xilinx/spartan3/dsp.rst

@@ -1,16 +1,25 @@
+.. _spartan3-dsp:
+
 DSP — Spartan 3A DSP, Spartan 6
 ###############################
 
+.. todo:: document
+
+
+Bitstream
+=========
+
+The data for a DSP is spread across the 4 bitstream tiles belonging to the corresponding ``INT`` tiles, in order from the bottom row.
 
-Bitstream — Spartan 3A DSP
-==========================
+Spartan 3A DSP
+--------------
 
 .. raw:: html
    :file: ../gen-xilinx-tile-xc3s-DSP.html
 
 
-Bitstream — Spartan 6
-=====================
+Spartan 6
+---------
 
 .. raw:: html
    :file: ../gen-xilinx-tile-xc6s-DSP.html

docs/xilinx/spartan3/index.rst

@@ -7,6 +7,8 @@ Xilinx Spartan 3 FPGAs
    :maxdepth: 2
    :caption: Contents:
 
+   intro
+   structure
    interconnect
    clb
    dsp