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_sources/xilinx/index.rst.txt

@@ -5,6 +5,12 @@ Xilinx FPGAs
    :maxdepth: 2
    :caption: Contents:
 
+   xc2000/index
+   xc3000/index
+   xc3000a/index
+   xc4000/index
+   xc4000a/index
+   xc4000h/index
    xc4000e/index
    xc4000ex/index
    xc4000xla/index

_sources/xilinx/xc2000/bidi.rst.txt

@@ -0,0 +1,44 @@
+Bidi buffers
+############
+
+
+``BIDIH``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIH.html
+
+
+``BIDIH.B``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIH.B.html
+
+
+``BIDIH.T``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIH.T.html
+
+
+``BIDIV``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIV.html
+
+
+``BIDIV.L``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIV.L.html
+
+
+``BIDIV.R``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-BIDIV.R.html

_sources/xilinx/xc2000/clb.rst.txt

@@ -0,0 +1,93 @@
+Configurable Logic Block
+########################
+
+
+``CLB``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.html
+
+
+``CLB.L``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.L.html
+
+
+``CLB.R``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.R.html
+
+
+``CLB.ML``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.ML.html
+
+
+``CLB.MR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.MR.html
+
+
+``CLB.B``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.B.html
+
+
+``CLB.BR1``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.BR1.html
+
+
+``CLB.BL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.BL.html
+
+
+``CLB.BR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.BR.html
+
+
+``CLB.T``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.T.html
+
+
+``CLB.TR1``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.TR1.html
+
+
+``CLB.TL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.TL.html
+
+
+``CLB.TR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc2k-CLB.TR.html

_sources/xilinx/xc2000/index.rst.txt

@@ -0,0 +1,11 @@
+XC2000
+######
+
+.. todo:: intro document, bitstream format, ...
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   clb
+   bidi

_sources/xilinx/xc3000/clb.rst.txt

@@ -0,0 +1,233 @@
+Configurable Logic Block
+########################
+
+
+``CLB.0``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.0.html
+
+
+``CLB.1``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.1.html
+
+
+``CLB.2``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.2.html
+
+
+``CLB.L.0``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.L.0.html
+
+
+``CLB.L.1``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.L.1.html
+
+
+``CLB.L.2``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.L.2.html
+
+
+``CLB.R.0``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.R.0.html
+
+
+``CLB.R.1``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.R.1.html
+
+
+``CLB.R.2``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.R.2.html
+
+
+``CLB.R.3``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.R.3.html
+
+
+``CLB.B.0``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.B.0.html
+
+
+``CLB.B.1``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.B.1.html
+
+
+``CLB.B.2``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.B.2.html
+
+
+``CLB.BL.0``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.BL.0.html
+
+
+``CLB.BL.1``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.BL.1.html
+
+
+``CLB.BL.2``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.BL.2.html
+
+
+``CLB.BLS.2``
+=============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.BLS.2.html
+
+
+``CLB.BR.0``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.BR.0.html
+
+
+``CLB.BRS.0``
+=============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.BRS.0.html
+
+
+``CLB.T.0``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.T.0.html
+
+
+``CLB.T.1``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.T.1.html
+
+
+``CLB.T.2``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.T.2.html
+
+
+``CLB.TS.0``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TS.0.html
+
+
+``CLB.TS.1``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TS.1.html
+
+
+``CLB.TS.2``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TS.2.html
+
+
+``CLB.TL.0``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TL.0.html
+
+
+``CLB.TL.1``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TL.1.html
+
+
+``CLB.TL.2``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TL.2.html
+
+
+``CLB.TLS.0``
+=============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TLS.0.html
+
+
+``CLB.TR.0``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TR.0.html
+
+
+``CLB.TR.1``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TR.1.html
+
+
+``CLB.TR.2``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TR.2.html
+
+
+``CLB.TRS.1``
+=============
+
+.. raw:: html
+   :file: ../gen/tile-xc3k-CLB.TRS.1.html