xpla3: reversed SHIFT stuff.

docs/xpla3/structure.rst

@@ -291,6 +291,8 @@ Each macrocell has a register.  It has:
 
   - LUT output
   - pad input buffer (so-called fast input register)
+  - the Q output of the previous register in the FB (wrapping from 0 to 15) (so-called fast shift register)
+  - the Q output of the next register in the FB (wrapping from 15 to 0) (so-called fast shift register)
 
 - clock or gate input routable from one of:
 
@@ -357,6 +359,12 @@ The fuses involved are:
   - ``LATCH``
   - ``DFFCE``
 
+- ``FB[i].MC[j].REG_D_IREG``: if programmed, and the ``REG_D_SHIFT`` fuse is not programmed, the register D input is connected to ``FB[i].MC[j].IOB.I``; if neither is programmed, the register D input is connected to ``FB[i].MC[j].LUT_OUT``
+- ``FB[i].MC[j].REG_D_SHIFT``: if programmed, the register D input is connected to the previous or next MC's register Q output; otherwise, the connection is determined by ``REG_D_IREG`` fuse
+- ``FB[i].MC[j].REG_D_SHIFT_DIR``: when the previous fuse is programmed, determines which MC's register Q output is connected to this register's D input
+
+  - ``UP``: D input connected to ``FB[i].MC[(j - 1) % 16].REG``
+  - ``DOWN``: D input connected to ``FB[i].MC[(j + 1) % 16].REG``
 
 The register works as follows::
 
@@ -384,10 +392,15 @@ The register works as follows::
     LCT4: FB[i].MC[j].CE = FB[i].LCT4;
     endcase
 
-    case(FB[i].MC[j].REG_D_MUX)
-    LUT: FB[i].MC[j].REG_D = FB[i].MC[j].LUT_OUT;
-    IBUF: FB[i].MC[j].REG_D = FB[i].MC[j].IOB.I;
-    endcase
+    if (FB[i].MC[j].REG_D_SHIFT)
+        case(FB[i].MC[j].REG_D_SHIFT_DIR)
+        UP: FB[i].MC[j].REG_D = FB[i].MC[(j - 1) % 16].REG;
+        DOWN: FB[i].MC[j].REG_D = FB[i].MC[(j + 1) % 16].REG;
+        endcase
+    else if (FB[i].MC[j].REG_D_IREG)
+        FB[i].MC[j].REG_D = FB[i].MC[j].IOB.I;
+    else
+        FB[i].MC[j].REG_D = FB[i].MC[j].LUT_OUT;
 
     initial FB[i].MC[j].REG = 0;
 
@@ -427,8 +440,6 @@ The register works as follows::
                 FB[i].MC[j].REG = FB[i].MC[j].REG_D;
     endcase
 
-.. todo:: there are unknown bits involved
-
 
 Macrocell and IOB outputs
 =========================

prjcombine_xilinx_recpld/src/bin/xcpld_finish_xpla3.rs

@@ -41,9 +41,9 @@ const JED_MC_BITS_IOB: &[(&str, usize)] = &[
     ("CLK_MUX", 0),
     ("CLK_MUX", 1),
     ("CLK_MUX", 2),
-    ("REG_D_MUX", 0),
-    ("UNK_REG_Q", 0),
-    ("UNK_SHIFT", 0),
+    ("REG_D_IREG", 0),
+    ("REG_D_SHIFT_DIR", 0),
+    ("REG_D_SHIFT", 0),
     ("IOB_ZIA_MUX", 0),
     ("RST_MUX", 0),
     ("RST_MUX", 1),
@@ -66,9 +66,9 @@ const JED_MC_BITS_BURIED: &[(&str, usize)] = &[
     ("CLK_MUX", 0),
     ("CLK_MUX", 1),
     ("CLK_MUX", 2),
-    ("REG_D_MUX", 0),
-    ("UNK_REG_Q", 0),
-    ("UNK_SHIFT", 0),
+    ("REG_D_IREG", 0),
+    ("REG_D_SHIFT_DIR", 0),
+    ("REG_D_SHIFT", 0),
     ("RST_MUX", 0),
     ("RST_MUX", 1),
     ("RST_MUX", 2),
@@ -249,17 +249,17 @@ fn extract_mc_bits(device: &Device, fpart: &FuzzDbPart, dd: &DevData) -> Tile<Bi
             continue;
         }
         tile.insert(
-            "REG_D_MUX",
-            extract_bool_to_enum(mcb.use_ireg.unwrap(), xlat_bit, "IBUF", "LUT"),
+            "REG_D_IREG",
+            extract_bool(mcb.use_ireg.unwrap(), xlat_bit),
             |_| true,
         );
         tile.insert(
-            "UNK_REG_Q",
-            extract_bool((mcb.use_ireg.unwrap().0 + 1, true), xlat_bit),
+            "REG_D_SHIFT_DIR",
+            extract_bool_to_enum((mcb.use_ireg.unwrap().0 + 1, true), xlat_bit, "DOWN", "UP"),
             |_| true,
         );
         tile.insert(
-            "UNK_SHIFT",
+            "REG_D_SHIFT",
             extract_bool((mcb.use_ireg.unwrap().0 + 2, true), xlat_bit),
             |_| true,
         );