Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

TC-CGEN-2.2 python test #37262

Open
wants to merge 24 commits into
base: master
Choose a base branch
from

Conversation

juandediosg
Copy link
Contributor

@juandediosg juandediosg commented Jan 28, 2025

Description

This PR is focused on implementing and validating the TC-CGEN-2.2
Fixes: project-chip/matter-test-scripts#404
Test plan: https://github.com/CHIP-Specifications/chip-test-plans/blob/master/src/cluster/General_Commissioning.adoc

Purpose

This test case validates the behavior of the failsafe timer during the commissioning process, focusing on its expiration, reset behavior, and interactions with commissioning-related commands. The test ensures that the failsafe behaves as expected in various scenarios and has been adapted to bypass waiting for the failsafe to expire, optimizing test execution in CI environments. This approach simulates real-world scenarios such as network misconfigurations, incorrect credentials, expired certificates, and other issues that might occur during commissioning.

Notes

This PR includes a workaround for the waits related to the failsafe timer expiration. As specified in the test plan, the original behavior expected a wait for the failsafe expiry. However, to improve CI testing times and avoid unnecessary delays, the failsafe timer is set to 0 seconds using the function expire_failsafe_timer().

Testing

To run the automated TC-CGEN-2.2 test, follow these steps:

  1. Ensure your environment is set up and the necessary dependencies are installed.
  2. Run the following command from the command line:

python3 src/python_testing/TC_CGEN_2_2.py --commissioning-method on-network --qr-code MT:-24J0AFN00KA0648G00 --int-arg PIXIT.CGEN.FailsafeExpiryLengthSeconds:20

To simulate CI
python3 src/python_testing/TC_CGEN_2_2.py --commissioning-method on-network --qr-code MT:-24J0AFN00KA0648G00 --PICS src/app/tests/suites/certification/ci-pics-values --int-arg PIXIT.CGEN.FailsafeExpiryLengthSeconds:1

Copy link

semanticdiff-com bot commented Jan 28, 2025

Review changes with  SemanticDiff

Changed Files
File Status
  src/python_testing/TC_CGEN_2_2.py  0% smaller

@github-actions github-actions bot added the tests label Jan 28, 2025
@juandediosg juandediosg changed the title Tc cgen 2 2 python test TC-CGEN-2.2 python test Jan 28, 2025
@juandediosg
Copy link
Contributor Author

juandediosg commented Jan 29, 2025

Currently exploring two improvements for the test:

- Handling the waits: The test has long waits, especially in the failsafe process. One option being explored is to minimize these waits in CI by arming the failsafe with a time=0 command, which would trigger the failsafe immediately without unnecessary delays.
- Step before 44: There’s also the need to add a step before 44 to remove TH2, which wasn’t accounted for in the original flow. This will ensure that the number of root certs returns to the expected state before proceeding.
Clean-up and refactoring: I’m also looking into cleaning up the test and refactoring certain parts of the code to improve

@juandediosg juandediosg marked this pull request as ready for review January 30, 2025 01:09
Copy link

PR #37262: Size comparison from b082219 to 36442c5

Full report (3 builds for cc32xx, stm32)
platform target config section b082219 36442c5 change % change
cc32xx air-purifier CC3235SF_LAUNCHXL FLASH 538413 538445 32 0.0
RAM 205192 205192 0 0.0
lock CC3235SF_LAUNCHXL FLASH 572277 572309 32 0.0
RAM 205344 205344 0 0.0
stm32 light STM32WB5MM-DK FLASH 482568 482600 32 0.0
RAM 144672 144672 0 0.0

Copy link

github-actions bot commented Jan 30, 2025

PR #37262: Size comparison from 3044eeb to f2664b2

Full report (71 builds for bl602, bl702, bl702l, cc13x4_26x4, cc32xx, cyw30739, efr32, esp32, linux, nrfconnect, nxp, psoc6, qpg, stm32, telink, tizen)
platform target config section 3044eeb f2664b2 change % change
bl602 lighting-app bl602+mfd+littlefs+rpc FLASH 1093546 1093546 0 0.0
RAM 103298 103298 0 0.0
bl702 lighting-app bl702+eth FLASH 650158 650158 0 0.0
RAM 25265 25265 0 0.0
bl702+wifi FLASH 828066 828066 0 0.0
RAM 13981 13981 0 0.0
bl706+mfd+rpc+littlefs FLASH 1056626 1056626 0 0.0
RAM 23861 23861 0 0.0
bl702l contact-sensor-app bl702l+mfd+littlefs FLASH 888060 888060 0 0.0
RAM 18504 18504 0 0.0
lighting-app bl702l+mfd+littlefs FLASH 971046 971046 0 0.0
RAM 16368 16368 0 0.0
cc13x4_26x4 lighting-app LP_EM_CC1354P10_6 FLASH 838000 838000 0 0.0
RAM 123464 123464 0 0.0
lock-ftd LP_EM_CC1354P10_6 FLASH 823420 823420 0 0.0
RAM 125344 125344 0 0.0
pump-app LP_EM_CC1354P10_6 FLASH 770644 770644 0 0.0
RAM 113804 113804 0 0.0
pump-controller-app LP_EM_CC1354P10_6 FLASH 754888 754888 0 0.0
RAM 114012 114012 0 0.0
cc32xx air-purifier CC3235SF_LAUNCHXL FLASH 538445 538445 0 0.0
RAM 205192 205192 0 0.0
lock CC3235SF_LAUNCHXL FLASH 572309 572309 0 0.0
RAM 205344 205344 0 0.0
cyw30739 light CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 679409 679409 0 0.0
RAM 78532 78532 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 699261 699261 0 0.0
RAM 81172 81172 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 699261 699261 0 0.0
RAM 81172 81172 0 0.0
CYW930739M2EVB-02 unknown 2040 2040 0 0.0
FLASH 656189 656189 0 0.0
RAM 73600 73600 0 0.0
light-switch CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 615793 615793 0 0.0
RAM 71516 71516 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 635421 635421 0 0.0
RAM 74060 74060 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 635421 635421 0 0.0
RAM 74060 74060 0 0.0
lock CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 635273 635273 0 0.0
RAM 74524 74524 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 654981 654981 0 0.0
RAM 77068 77068 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 654981 654981 0 0.0
RAM 77068 77068 0 0.0
thermostat CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 611709 611709 0 0.0
RAM 68612 68612 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 631569 631569 0 0.0
RAM 71252 71252 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 631569 631569 0 0.0
RAM 71252 71252 0 0.0
efr32 lock-app BRD4187C FLASH 936232 936232 0 0.0
RAM 159904 159904 0 0.0
BRD4338a FLASH 729900 729892 -8 -0.0
RAM 234764 234764 0 0.0
window-app BRD4187C FLASH 1029256 1029248 -8 -0.0
RAM 128040 128040 0 0.0
esp32 all-clusters-app c3devkit DRAM 97296 97296 0 0.0
FLASH 1577036 1577036 0 0.0
IRAM 83820 83820 0 0.0
m5stack DRAM 116092 116092 0 0.0
FLASH 1544978 1544978 0 0.0
IRAM 117039 117039 0 0.0
linux air-purifier-app debug unknown 4760 4760 0 0.0
FLASH 2708921 2708921 0 0.0
RAM 132816 132816 0 0.0
all-clusters-app debug unknown 5568 5568 0 0.0
FLASH 5974944 5974944 0 0.0
RAM 531632 531632 0 0.0
all-clusters-minimal-app debug unknown 5464 5464 0 0.0
FLASH 5323630 5323630 0 0.0
RAM 242744 242744 0 0.0
bridge-app debug unknown 5480 5480 0 0.0
FLASH 4681818 4681818 0 0.0
RAM 221480 221480 0 0.0
chip-tool debug unknown 6120 6120 0 0.0
FLASH 13096130 13096130 0 0.0
RAM 596770 596770 0 0.0
chip-tool-ipv6only arm64 unknown 21848 21848 0 0.0
FLASH 1116208 1116208 0 0.0
RAM 648496 648496 0 0.0
fabric-admin debug unknown 5808 5808 0 0.0
FLASH 11388177 11388177 0 0.0
RAM 596554 596554 0 0.0
fabric-bridge-app debug unknown 4736 4736 0 0.0
FLASH 4506416 4506416 0 0.0
RAM 208664 208664 0 0.0
fabric-sync debug unknown 4976 4976 0 0.0
FLASH 5612789 5612789 0 0.0
RAM 483536 483536 0 0.0
lighting-app debug+rpc+ui unknown 6144 6144 0 0.0
FLASH 5624577 5624577 0 0.0
RAM 231760 231760 0 0.0
lock-app debug unknown 5416 5416 0 0.0
FLASH 4730932 4730932 0 0.0
RAM 207728 207728 0 0.0
ota-provider-app debug unknown 4776 4776 0 0.0
FLASH 4359476 4359476 0 0.0
RAM 201368 201368 0 0.0
ota-requestor-app debug unknown 4728 4728 0 0.0
FLASH 4496948 4496948 0 0.0
RAM 205952 205952 0 0.0
shell debug unknown 4256 4256 0 0.0
FLASH 3004845 3004845 0 0.0
RAM 160504 160504 0 0.0
thermostat-no-ble arm64 unknown 9536 9536 0 0.0
FLASH 4098704 4098704 0 0.0
RAM 246144 246144 0 0.0
tv-app debug unknown 5744 5744 0 0.0
FLASH 5952389 5952389 0 0.0
RAM 606936 606936 0 0.0
tv-casting-app debug unknown 5320 5320 0 0.0
FLASH 11269741 11269741 0 0.0
RAM 710896 710896 0 0.0
nrfconnect all-clusters-app nrf52840dk_nrf52840 FLASH 906972 906972 0 0.0
RAM 142395 142395 0 0.0
nrf7002dk_nrf5340_cpuapp FLASH 901532 901532 0 0.0
RAM 124739 124739 0 0.0
all-clusters-minimal-app nrf52840dk_nrf52840 FLASH 845696 845696 0 0.0
RAM 141323 141323 0 0.0
nxp contact k32w0+release FLASH 584288 584288 0 0.0
RAM 70860 70860 0 0.0
mcxw71+release FLASH 599632 599632 0 0.0
RAM 63080 63080 0 0.0
light k32w0+release FLASH 610732 610732 0 0.0
RAM 70252 70252 0 0.0
k32w1+release FLASH 685192 685192 0 0.0
RAM 48664 48664 0 0.0
lock mcxw71+release FLASH 748664 748664 0 0.0
RAM 67476 67476 0 0.0
psoc6 all-clusters cy8ckit_062s2_43012 FLASH 1646372 1646372 0 0.0
RAM 211560 211560 0 0.0
all-clusters-minimal cy8ckit_062s2_43012 FLASH 1553148 1553148 0 0.0
RAM 208376 208376 0 0.0
light cy8ckit_062s2_43012 FLASH 1468828 1468828 0 0.0
RAM 200352 200352 0 0.0
lock cy8ckit_062s2_43012 FLASH 1466860 1466860 0 0.0
RAM 224688 224688 0 0.0
qpg lighting-app qpg6105+debug FLASH 661984 661984 0 0.0
RAM 105204 105204 0 0.0
lock-app qpg6105+debug FLASH 619788 619788 0 0.0
RAM 99648 99648 0 0.0
stm32 light STM32WB5MM-DK FLASH 482600 482600 0 0.0
RAM 144672 144672 0 0.0
telink bridge-app tlsr9258a FLASH 681290 681290 0 0.0
RAM 91084 91084 0 0.0
contact-sensor-app tlsr9528a_retention FLASH 621322 621322 0 0.0
RAM 31484 31484 0 0.0
light-app-ota-compress-lzma-shell-factory-data tl3218x FLASH 770160 770160 0 0.0
RAM 49344 49344 0 0.0
light-app-ota-shell-factory-data tl7218x FLASH 774590 774590 0 0.0
RAM 99648 99648 0 0.0
light-switch-app-ota-compress-lzma-shell-factory-data tlsr9528a FLASH 708494 708494 0 0.0
RAM 73376 73376 0 0.0
lighting-app-ota-factory-data tlsr9118bdk40d FLASH 625592 625592 0 0.0
RAM 142016 142016 0 0.0
lighting-app-ota-rpc-factory-data-4mb tlsr9518adk80d FLASH 812972 812972 0 0.0
RAM 99560 99560 0 0.0
tizen all-clusters-app arm unknown 5116 5116 0 0.0
FLASH 1751892 1751892 0 0.0
RAM 93524 93524 0 0.0
chip-tool-ubsan arm unknown 11408 11408 0 0.0
FLASH 18696094 18696094 0 0.0
RAM 8183744 8183744 0 0.0

@@ -0,0 +1,796 @@
#
# Copyright (c) 2022 Project CHIP Authors
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change
# Copyright (c) 2022 Project CHIP Authors
# Copyright (c) 2025 Project CHIP Authors

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed: Line updated



class TC_CGEN_2_2(MatterBaseTest):
async def FindAndEstablishPase(self, longDiscriminator: int, setupPinCode: int, nodeid: int, dev_ctrl: ChipDeviceCtrl = None):
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can this be replaced with the FindOrEstablishPASESession function from ChipDeviceCtrl.py to avoid duplication?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed: Replaced with FindOrEstablishPASESession function to avoid duplication

def steps_TC_CGEN_2_2(self) -> list[TestStep]:
steps = [
TestStep(0, "Commissioning, already done", is_commissioning=True),
TestStep(1, """TH1 reads the TrustedRootCertificates attribute from the Node Operational Credentials cluster
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

None of these are multiline, so I think single quotes are fine here.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed

async def test_TC_CGEN_2_2(self):
cluster_opcreds = Clusters.OperationalCredentials
cluster_cgen = Clusters.GeneralCommissioning
# maxFailsafe_tmp = 60
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change
# maxFailsafe_tmp = 60

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed: Line removed.


self.step(0)

# Read the Spteps
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change
# Read the Spteps
# Read the Steps

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed: Line updated.

logger.info("Step 38 skipped: Saving Tstart (current wall time clock) is bypassed due to failsafe expiration workaround.")

self.step(39)
trusted_root_list_original_updated = await self.read_single_attribute_check_success(
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

this isn't from the test plan...

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed: Function removed as it wasn't part of the test plan.

logger.info(
f'Step #39 - The updated size of the num_trusted_roots_original list: {trusted_root_list_original_size_updated}')

# Flow generates a new TrustedRootCertificate - Request CSR (Certificate Signing Request) and update NOC (Node Operational Certificate)
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

can re-use the previously generated one.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed: Reused cert created in step 5.

"Step #31 - Unexpected number of entries in the TrustedRootCertificates table after update")

self.step(41)
# Step 41 - Skipped
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

keep this in for cert testing, skip for CI.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed: Implemented CI and Cert test flows

# which immediately expires the failsafe timer (sets it to 0), bypassing the natural wait and speeding up the test execution.

# This function bypasses the wait for the FailsafeTimer to expire for TH1 as originally defined in the test plan.
resp = await self.expire_failsafe_timer(dev_ctrl=self.default_controller, node_id=self.dut_node_id)
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

gate on CI

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed: Implemented CI and Cert test flows

cmd = Clusters.OperationalCredentials.Commands.RemoveFabric(fabricIndex=fabric_idx)
await self.send_single_cmd(dev_ctrl=TH2, node_id=newNodeId+1, cmd=cmd)

# The expected number of root certificates should be 1 after removing the fabric
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change
# The expected number of root certificates should be 1 after removing the fabric
# The expected number of root certificates should be numTrustedRootsOriginal after removing the fabric

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed: Comment updated.

@juandediosg
Copy link
Contributor Author

juandediosg commented Feb 10, 2025

Final version. Below are the highlighted updates, changes, and refactoring:

Note: The script has passed CI job checkpoints, including Lint code base, Restyled, etc.

  • Refactored and cleaned up.
  • Updated code and logger comments.
  • For the CI flow, the logic was implemented with the is_pics_sdk_ci_only to correctly handle test depending on environment.
  • Adjusted the sequence between maxFailSafe and PIXIT.CGEN.FailsafeExpiryLengthSeconds.
  • In the CERT tests, failsafe_expiration_seconds = 20 was set for the waits, while for CI, the expire_failsafe_timer function was used with a small re-arm of the timer (1 second) to correctly verify the timer expiration.
  • Reused previously generated certificates.
  • Steps 3, 4, and 5 were wrapped into one function with boolean control, while steps 8 and 9 were grouped into another function with boolean control.
  • For step 22, the code remained unchanged, and it was suggested not to modify the SetSkipCommissioningComplete(True) logic, as it resulted in an error at step 29.
  • Implemented FindOrEstablishPASESession function from ChipDeviceCtrl.py to avoid duplication.
  • Implemented Mobly asserts to improve error handling and overall test framework consistency.
  • Updated logic on sequence of steps 29-36 to align with the new optimizations.

cluster_opcreds = Clusters.OperationalCredentials
cluster_cgen = Clusters.GeneralCommissioning

async def expire_failsafe_timer(self, dev_ctrl, node_id, expiration_time_seconds):
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

naming - normally setting the failsafe to 0 is "expiring" or "disarming" the failsafe timer. Any non-zero value is normally "arming" the failsafe timer for that time. a failsafe of 0 is treated as an immediate disarm.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The function was designed based on your previous suggestion, which recommended a short duration of 1 second to test the expiration of the failsafe timer. To facilitate testing in continuous integration (CI) environments, I hardcoded the 1-second expiration time to speed up and improve the efficiency of the tests. However, the function remains flexible, allowing the expiration_time_seconds to be set to any value, making it easy to adjust for various testing needs or scenarios.

Additionally, to clarify the function's purpose, I have renamed it to set_failsafe_timer, which better indicates that this function is used to configure the failsafe timer.

response: The response from the command sent to the device.
'''
# Buffer for latency
buffer_latency = .5
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

If you use 0 to disarm, you shouldn't need a buffer here.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The function was designed to always arm and expire the failsafe timer with a positive expiration time. To ensure accurate expiration even with short durations like 1 second, I added a latency buffer to account for potential delays in CI environments. This helps ensure the timer expires correctly, considering possible network or processing latencies

if c_time is None:
c_time = time.time()

formatted_time = (
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I'm guessing this is for logging, but does having the UTC time help here, or would it make more sense to have the number of elapsed ms (or us or whatever) since t_start?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I have removed the function that formatted the UTC time, and now I am logging the elapsed_time in milliseconds since t_start in steps 41 and 43 for better precision and relevance to the test flow.

logger.info(f'Step #6: The updated size of the num_trusted_roots_original list: {trusted_root_list_original_size_updated}')

self.step(7)
if self.is_pics_sdk_ci_only:
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think this might actually be fine for ALL devices - you're still seeing the failsafe expire on its timer vs. forcing it to 0 explicitly. ie, it might make sense to just adjust the test to set this to 1s before waiting.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

In the CI flow, the failsafe expiration time is explicitly set to 1 second before invoking the set_failsafe_timer function, ensuring the timer expires as expected.
Would like to make any adjustments to this approach?

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

yes, the test is just trying to ensure that the dut times out correctly vs. being forced to expire. We don't have to wait out the original time even in cert - you can set to this 1s for both CI and for real devices and the test results are still valid because the expiration happens as a result of a timer, even if the timer is small. Just add a test step to the test plan, and it cuts down the wait time for this test during both CI and certification.

async def test_TC_CGEN_2_2(self):

# PIXIT.CGEN.FailsafeExpiryLengthSeconds:
# Timeout used in test steps to verify failsafe. Must be less than DUT MaxCumulativeFailsafeSeconds
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can you hook this up to a user parameter? https://project-chip.github.io/connectedhomeip-doc/testing/python.html#pics-and-pixits. that will let testers adjust this if required.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Hooked failsafe_expiration_seconds to user parameter PIXIT.CGEN.FailsafeExpiryLengthSeconds for flexible configuration based on CI or Cert flow

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can you please add a default here? And a check that it's less than MaxCumulativeFailsafeSeconds

logger.info('Step #15 - TH2 successfully establish PASE session completed')

self.step(16)
logger.info('Step #16 - TH2 Generating a new CSR to update the root certificate...')
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I meant the process of generating a new cert. But actually, as long as you're always adding a cert that's not the one on the device, you should be able to re-use the first certificate instead of doing this dance every time.

logger.info(f'Step #20 - TH1 Original size of the trusted_root list: {trusted_roots_list_size}')

self.step(21)
# Commissioning stage numbers - we should find a better way to match these to the C++ code
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It looks like the folks doing some of the new features plumbed through the functions required to do this using the commissioning parameters. Can you take a look at CGEN-2.5 (I James used it a few places). https://github.com/project-chip/connectedhomeip/blob/master/src/python_testing/TC_CGEN_2_5.py#L88. That will make this much neater, and I think it means you don't need to use the test commissioner.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Currently, it is not possible to implement the function self.commission_devices() due to structural limitations. The use of CommissionDeviceTest conflicts with the requirement of having only one subclass of MatterBaseTest in the main file. Although the function is implemented in TC_CGEN_2_5.py, the test fails because the function cannot be found. Therefore, maintaining the current implementation is the most viable option for now.

Copy link

@jtrejoespinoza-grid jtrejoespinoza-grid left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Changes requested updated.

Copy link

@jtrejoespinoza-grid jtrejoespinoza-grid left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Mentioned issues addressed.

Copy link

github-actions bot commented Feb 14, 2025

PR #37262: Size comparison from ecb3c14 to 722f4e2

Full report (72 builds for bl602, bl702, bl702l, cc13x4_26x4, cc32xx, cyw30739, efr32, esp32, linux, nrfconnect, nxp, psoc6, qpg, stm32, telink, tizen)
platform target config section ecb3c14 722f4e2 change % change
bl602 lighting-app bl602+mfd+littlefs+rpc FLASH 1095960 1095960 0 0.0
RAM 94906 94906 0 0.0
bl702 lighting-app bl702+eth FLASH 652080 652080 0 0.0
RAM 33633 33633 0 0.0
bl702+wifi FLASH 828572 828572 0 0.0
RAM 22341 22341 0 0.0
bl706+mfd+rpc+littlefs FLASH 1061718 1061718 0 0.0
RAM 32285 32285 0 0.0
bl702l contact-sensor-app bl702l+mfd+littlefs FLASH 892592 892592 0 0.0
RAM 26912 26912 0 0.0
lighting-app bl702l+mfd+littlefs FLASH 975962 975962 0 0.0
RAM 24752 24752 0 0.0
cc13x4_26x4 lighting-app LP_EM_CC1354P10_6 FLASH 815204 815204 0 0.0
RAM 120352 120352 0 0.0
lock-ftd LP_EM_CC1354P10_6 FLASH 823832 823832 0 0.0
RAM 125360 125360 0 0.0
pump-app LP_EM_CC1354P10_6 FLASH 770992 770992 0 0.0
RAM 113820 113820 0 0.0
pump-controller-app LP_EM_CC1354P10_6 FLASH 755260 755260 0 0.0
RAM 114028 114028 0 0.0
cc32xx air-purifier CC3235SF_LAUNCHXL FLASH 538894 538894 0 0.0
RAM 205208 205208 0 0.0
lock CC3235SF_LAUNCHXL FLASH 572766 572766 0 0.0
RAM 205360 205360 0 0.0
cyw30739 light CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 656501 656501 0 0.0
RAM 75420 75420 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 676361 676361 0 0.0
RAM 78060 78060 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 676361 676361 0 0.0
RAM 78060 78060 0 0.0
CYW930739M2EVB-02 unknown 2040 2040 0 0.0
FLASH 633285 633285 0 0.0
RAM 70488 70488 0 0.0
light-switch CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 616117 616117 0 0.0
RAM 71532 71532 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 635753 635753 0 0.0
RAM 74076 74076 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 635753 635753 0 0.0
RAM 74076 74076 0 0.0
lock CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 635621 635621 0 0.0
RAM 74540 74540 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 655337 655337 0 0.0
RAM 77084 77084 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 655337 655337 0 0.0
RAM 77084 77084 0 0.0
thermostat CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 611969 611969 0 0.0
RAM 68628 68628 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 631829 631829 0 0.0
RAM 71268 71268 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 631829 631829 0 0.0
RAM 71268 71268 0 0.0
efr32 lock-app BRD4187C FLASH 937264 937264 0 0.0
RAM 159908 159908 0 0.0
BRD4338a FLASH 730592 730584 -8 -0.0
RAM 234720 234720 0 0.0
window-app BRD4187C FLASH 1029856 1029856 0 0.0
RAM 128012 128012 0 0.0
esp32 all-clusters-app c3devkit DRAM 97312 97312 0 0.0
FLASH 1581680 1581680 0 0.0
IRAM 83820 83820 0 0.0
m5stack DRAM 116100 116100 0 0.0
FLASH 1549606 1549606 0 0.0
IRAM 117039 117039 0 0.0
linux air-purifier-app debug unknown 4760 4712 -48 -1.0
FLASH 2708747 2648901 -59846 -2.2
RAM 132784 111600 -21184 -16.0
all-clusters-app debug unknown 5568 5520 -48 -0.9
FLASH 5975210 5915332 -59878 -1.0
RAM 531600 510416 -21184 -4.0
all-clusters-minimal-app debug unknown 5464 5416 -48 -0.9
FLASH 5322754 5262876 -59878 -1.1
RAM 242712 221528 -21184 -8.7
bridge-app debug unknown 5480 5432 -48 -0.9
FLASH 4681398 4621552 -59846 -1.3
RAM 221448 200264 -21184 -9.6
chip-tool debug unknown 6120 6088 -32 -0.5
FLASH 13098960 13071206 -27754 -0.2
RAM 596578 596482 -96 -0.0
chip-tool-ipv6only arm64 unknown 21816 21816 0 0.0
FLASH 11162224 11137776 -24448 -0.2
RAM 648256 648160 -96 -0.0
fabric-admin debug unknown 5808 5776 -32 -0.6
FLASH 11387977 11359987 -27990 -0.2
RAM 596362 596266 -96 -0.0
fabric-bridge-app debug unknown 4736 4680 -56 -1.2
FLASH 4506720 4446874 -59846 -1.3
RAM 208632 187480 -21152 -10.1
fabric-sync debug unknown 4976 4936 -40 -0.8
FLASH 5612965 5563813 -49152 -0.9
RAM 483504 467024 -16480 -3.4
lighting-app debug+rpc+ui unknown 6152 6104 -48 -0.8
FLASH 5484513 5424673 -59840 -1.1
RAM 225392 204208 -21184 -9.4
lock-app debug unknown 5416 5384 -32 -0.6
FLASH 4730794 4681596 -49198 -1.0
RAM 207696 191216 -16480 -7.9
ota-provider-app debug unknown 4776 4720 -56 -1.2
FLASH 4359828 4299982 -59846 -1.4
RAM 201336 180184 -21152 -10.5
ota-requestor-app debug unknown 4728 4672 -56 -1.2
FLASH 4497204 4437358 -59846 -1.3
RAM 205920 184768 -21152 -10.3
shell debug unknown 4256 4216 -40 -0.9
FLASH 3005468 2950060 -55408 -1.8
RAM 160552 144040 -16512 -10.3
thermostat-no-ble arm64 unknown 9512 9512 0 0.0
FLASH 4096488 4039880 -56608 -1.4
RAM 246024 228528 -17496 -7.1
tv-app debug unknown 5744 5712 -32 -0.6
FLASH 5951893 5902693 -49200 -0.8
RAM 606904 590424 -16480 -2.7
tv-casting-app debug unknown 5320 5288 -32 -0.6
FLASH 11271725 11243757 -27968 -0.2
RAM 710864 710640 -224 -0.0
nrfconnect all-clusters-app nrf52840dk_nrf52840 FLASH 907464 907464 0 0.0
RAM 142411 142411 0 0.0
nrf7002dk_nrf5340_cpuapp FLASH 901920 901920 0 0.0
RAM 124755 124755 0 0.0
all-clusters-minimal-app nrf52840dk_nrf52840 FLASH 846084 846084 0 0.0
RAM 141339 141339 0 0.0
nxp contact k32w0+release FLASH 584752 584752 0 0.0
RAM 70876 70876 0 0.0
mcxw71+release FLASH 600208 600208 0 0.0
RAM 63096 63096 0 0.0
light k32w0+release FLASH 611076 611076 0 0.0
RAM 70268 70268 0 0.0
k32w1+release FLASH 685512 685512 0 0.0
RAM 48680 48680 0 0.0
lock mcxw71+release FLASH 749024 749024 0 0.0
RAM 67500 67500 0 0.0
psoc6 all-clusters cy8ckit_062s2_43012 FLASH 1646756 1646756 0 0.0
RAM 211576 211576 0 0.0
all-clusters-minimal cy8ckit_062s2_43012 FLASH 1553524 1553524 0 0.0
RAM 208392 208392 0 0.0
light cy8ckit_062s2_43012 FLASH 1439196 1439196 0 0.0
RAM 197144 197144 0 0.0
lock cy8ckit_062s2_43012 FLASH 1467412 1467412 0 0.0
RAM 224704 224704 0 0.0
qpg lighting-app qpg6105+debug FLASH 662340 662340 0 0.0
RAM 105220 105220 0 0.0
lock-app qpg6105+debug FLASH 620136 620136 0 0.0
RAM 99664 99664 0 0.0
stm32 light STM32WB5MM-DK FLASH 459736 459736 0 0.0
RAM 141568 141568 0 0.0
telink bridge-app tl7218x FLASH 665226 665226 0 0.0
RAM 90828 90828 0 0.0
contact-sensor-app tlsr9528a_retention FLASH 621908 621908 0 0.0
RAM 31488 31488 0 0.0
light-app-ota-shell-factory-data tl3218x FLASH 745418 745418 0 0.0
RAM 40496 40496 0 0.0
tl7218x FLASH 753974 753974 0 0.0
RAM 97632 97632 0 0.0
light-switch-app-ota-compress-lzma-factory-data tl7218x_retention FLASH 680678 680678 0 0.0
RAM 52192 52192 0 0.0
light-switch-app-ota-compress-lzma-shell-factory-data tlsr9528a FLASH 709240 709240 0 0.0
RAM 73400 73400 0 0.0
lighting-app-ota-factory-data tlsr9118bdk40d FLASH 600796 600796 0 0.0
RAM 138912 138912 0 0.0
lighting-app-ota-rpc-factory-data-4mb tlsr9518adk80d FLASH 788928 788928 0 0.0
RAM 96488 96488 0 0.0
tizen all-clusters-app arm unknown 5104 5104 0 0.0
FLASH 1751708 1751708 0 0.0
RAM 93508 93508 0 0.0
chip-tool-ubsan arm unknown 11396 11396 0 0.0
FLASH 18683110 18683334 224 0.0
RAM 8181084 8181084 0 0.0

Copy link

github-actions bot commented Feb 14, 2025

PR #37262: Size comparison from ecb3c14 to b1bb5a4

Full report (72 builds for bl602, bl702, bl702l, cc13x4_26x4, cc32xx, cyw30739, efr32, esp32, linux, nrfconnect, nxp, psoc6, qpg, stm32, telink, tizen)
platform target config section ecb3c14 b1bb5a4 change % change
bl602 lighting-app bl602+mfd+littlefs+rpc FLASH 1095960 1096002 42 0.0
RAM 94906 94906 0 0.0
bl702 lighting-app bl702+eth FLASH 652080 652380 300 0.0
RAM 33633 33633 0 0.0
bl702+wifi FLASH 828572 828614 42 0.0
RAM 22341 22341 0 0.0
bl706+mfd+rpc+littlefs FLASH 1061718 1061760 42 0.0
RAM 32285 32285 0 0.0
bl702l contact-sensor-app bl702l+mfd+littlefs FLASH 892592 892634 42 0.0
RAM 26912 26912 0 0.0
lighting-app bl702l+mfd+littlefs FLASH 975962 976004 42 0.0
RAM 24752 24752 0 0.0
cc13x4_26x4 lighting-app LP_EM_CC1354P10_6 FLASH 815204 815468 264 0.0
RAM 120352 120352 0 0.0
lock-ftd LP_EM_CC1354P10_6 FLASH 823832 824096 264 0.0
RAM 125360 125360 0 0.0
pump-app LP_EM_CC1354P10_6 FLASH 770992 771248 256 0.0
RAM 113820 113820 0 0.0
pump-controller-app LP_EM_CC1354P10_6 FLASH 755260 755516 256 0.0
RAM 114028 114028 0 0.0
cc32xx air-purifier CC3235SF_LAUNCHXL FLASH 538894 538998 104 0.0
RAM 205208 205208 0 0.0
lock CC3235SF_LAUNCHXL FLASH 572766 572870 104 0.0
RAM 205360 205360 0 0.0
cyw30739 light CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 656501 656597 96 0.0
RAM 75420 75420 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 676361 676457 96 0.0
RAM 78060 78060 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 676361 676457 96 0.0
RAM 78060 78060 0 0.0
CYW930739M2EVB-02 unknown 2040 2040 0 0.0
FLASH 633285 633381 96 0.0
RAM 70488 70488 0 0.0
light-switch CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 616117 616213 96 0.0
RAM 71532 71532 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 635753 635849 96 0.0
RAM 74076 74076 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 635753 635849 96 0.0
RAM 74076 74076 0 0.0
lock CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 635621 635717 96 0.0
RAM 74540 74540 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 655337 655433 96 0.0
RAM 77084 77084 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 655337 655433 96 0.0
RAM 77084 77084 0 0.0
thermostat CYW30739B2-P5-EVK-01 unknown 2040 2040 0 0.0
FLASH 611969 612065 96 0.0
RAM 68628 68628 0 0.0
CYW30739B2-P5-EVK-02 unknown 2040 2040 0 0.0
FLASH 631829 631925 96 0.0
RAM 71268 71268 0 0.0
CYW30739B2-P5-EVK-03 unknown 2040 2040 0 0.0
FLASH 631829 631925 96 0.0
RAM 71268 71268 0 0.0
efr32 lock-app BRD4187C FLASH 937264 937424 160 0.0
RAM 159908 159916 8 0.0
BRD4338a FLASH 730592 731696 1104 0.2
RAM 234720 234772 52 0.0
window-app BRD4187C FLASH 1029856 1030016 160 0.0
RAM 128012 128020 8 0.0
esp32 all-clusters-app c3devkit DRAM 97312 97312 0 0.0
FLASH 1581680 1581788 108 0.0
IRAM 83820 83820 0 0.0
m5stack DRAM 116100 116100 0 0.0
FLASH 1549606 1549762 156 0.0
IRAM 117039 117039 0 0.0
linux air-purifier-app debug unknown 4760 4712 -48 -1.0
FLASH 2708747 2649195 -59552 -2.2
RAM 132784 111600 -21184 -16.0
all-clusters-app debug unknown 5568 5520 -48 -0.9
FLASH 5975210 5915628 -59582 -1.0
RAM 531600 510416 -21184 -4.0
all-clusters-minimal-app debug unknown 5464 5416 -48 -0.9
FLASH 5322754 5263172 -59582 -1.1
RAM 242712 221528 -21184 -8.7
bridge-app debug unknown 5480 5432 -48 -0.9
FLASH 4681398 4621848 -59550 -1.3
RAM 221448 200264 -21184 -9.6
chip-tool debug unknown 6120 6088 -32 -0.5
FLASH 13098960 13071502 -27458 -0.2
RAM 596578 596482 -96 -0.0
chip-tool-ipv6only arm64 unknown 21816 21816 0 0.0
FLASH 11162224 11138080 -24144 -0.2
RAM 648256 648184 -72 -0.0
fabric-admin debug unknown 5808 5776 -32 -0.6
FLASH 11387977 11360283 -27694 -0.2
RAM 596362 596266 -96 -0.0
fabric-bridge-app debug unknown 4736 4680 -56 -1.2
FLASH 4506720 4447170 -59550 -1.3
RAM 208632 187480 -21152 -10.1
fabric-sync debug unknown 4976 4936 -40 -0.8
FLASH 5612965 5564101 -48864 -0.9
RAM 483504 467024 -16480 -3.4
lighting-app debug+rpc+ui unknown 6152 6104 -48 -0.8
FLASH 5484513 5424961 -59552 -1.1
RAM 225392 204208 -21184 -9.4
lock-app debug unknown 5416 5384 -32 -0.6
FLASH 4730794 4681892 -48902 -1.0
RAM 207696 191216 -16480 -7.9
ota-provider-app debug unknown 4776 4720 -56 -1.2
FLASH 4359828 4300278 -59550 -1.4
RAM 201336 180184 -21152 -10.5
ota-requestor-app debug unknown 4728 4672 -56 -1.2
FLASH 4497204 4437654 -59550 -1.3
RAM 205920 184768 -21152 -10.3
shell debug unknown 4256 4216 -40 -0.9
FLASH 3005468 2950364 -55104 -1.8
RAM 160552 144040 -16512 -10.3
thermostat-no-ble arm64 unknown 9512 9512 0 0.0
FLASH 4096488 4040184 -56304 -1.4
RAM 246024 228552 -17472 -7.1
tv-app debug unknown 5744 5712 -32 -0.6
FLASH 5951893 5902981 -48912 -0.8
RAM 606904 590424 -16480 -2.7
tv-casting-app debug unknown 5320 5288 -32 -0.6
FLASH 11271725 11244045 -27680 -0.2
RAM 710864 710640 -224 -0.0
nrfconnect all-clusters-app nrf52840dk_nrf52840 FLASH 907464 907556 92 0.0
RAM 142411 142411 0 0.0
nrf7002dk_nrf5340_cpuapp FLASH 901920 901960 40 0.0
RAM 124755 124755 0 0.0
all-clusters-minimal-app nrf52840dk_nrf52840 FLASH 846084 846172 88 0.0
RAM 141339 141339 0 0.0
nxp contact k32w0+release FLASH 584752 585072 320 0.1
RAM 70876 70876 0 0.0
mcxw71+release FLASH 600208 600544 336 0.1
RAM 63096 63096 0 0.0
light k32w0+release FLASH 611076 611380 304 0.0
RAM 70268 70268 0 0.0
k32w1+release FLASH 685512 685848 336 0.0
RAM 48680 48680 0 0.0
lock mcxw71+release FLASH 749024 749360 336 0.0
RAM 67500 67500 0 0.0
psoc6 all-clusters cy8ckit_062s2_43012 FLASH 1646756 1646868 112 0.0
RAM 211576 211576 0 0.0
all-clusters-minimal cy8ckit_062s2_43012 FLASH 1553524 1553620 96 0.0
RAM 208392 208392 0 0.0
light cy8ckit_062s2_43012 FLASH 1439196 1439308 112 0.0
RAM 197144 197144 0 0.0
lock cy8ckit_062s2_43012 FLASH 1467412 1467508 96 0.0
RAM 224704 224704 0 0.0
qpg lighting-app qpg6105+debug FLASH 662340 662436 96 0.0
RAM 105220 105220 0 0.0
lock-app qpg6105+debug FLASH 620136 620232 96 0.0
RAM 99664 99664 0 0.0
stm32 light STM32WB5MM-DK FLASH 459736 460008 272 0.1
RAM 141568 141568 0 0.0
telink bridge-app tl7218x FLASH 665226 665266 40 0.0
RAM 90828 90828 0 0.0
contact-sensor-app tlsr9528a_retention FLASH 621908 621948 40 0.0
RAM 31488 31488 0 0.0
light-app-ota-shell-factory-data tl3218x FLASH 745418 745458 40 0.0
RAM 40496 40496 0 0.0
tl7218x FLASH 753974 754014 40 0.0
RAM 97632 97632 0 0.0
light-switch-app-ota-compress-lzma-factory-data tl7218x_retention FLASH 680678 680718 40 0.0
RAM 52192 52192 0 0.0
light-switch-app-ota-compress-lzma-shell-factory-data tlsr9528a FLASH 709240 709280 40 0.0
RAM 73400 73400 0 0.0
lighting-app-ota-factory-data tlsr9118bdk40d FLASH 600796 600836 40 0.0
RAM 138912 138912 0 0.0
lighting-app-ota-rpc-factory-data-4mb tlsr9518adk80d FLASH 788928 788968 40 0.0
RAM 96488 96488 0 0.0
tizen all-clusters-app arm unknown 5104 5104 0 0.0
FLASH 1751708 1751824 116 0.0
RAM 93508 93508 0 0.0
chip-tool-ubsan arm unknown 11396 11396 0 0.0
FLASH 18683110 18683262 152 0.0
RAM 8181084 8181192 108 0.0

async def test_TC_CGEN_2_2(self):

# PIXIT.CGEN.FailsafeExpiryLengthSeconds:
# Timeout used in test steps to verify failsafe. Must be less than DUT MaxCumulativeFailsafeSeconds
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can you please add a default here? And a check that it's less than MaxCumulativeFailsafeSeconds

logger.info(f'Step #6: The updated size of the num_trusted_roots_original list: {trusted_root_list_original_size_updated}')

self.step(7)
if self.is_pics_sdk_ci_only:
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

yes, the test is just trying to ensure that the dut times out correctly vs. being forced to expire. We don't have to wait out the original time even in cert - you can set to this 1s for both CI and for real devices and the test results are still valid because the expiration happens as a result of a timer, even if the timer is small. Just add a test step to the test plan, and it cuts down the wait time for this test during both CI and certification.

# Verify that failsafe_timeout_less_than_max is less than max_fail_safe
asserts.assert_less(failsafe_timeout_less_than_max, maxFailsafe)

if self.is_pics_sdk_ci_only:
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I'm not sure I see the difference here between the CI and the cert test.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

To manage timeout behavior more effectively, we approach CI and Cert tests differently. Both are currently set to 1 second, but they handle timeout a bit differently:

  • CI: PIXIT.CGEN.FailsafeExpiryLengthSeconds PIXIT value, to adjust the timeout duration based on the CI and specs req.

  • [FIXED] Cert: FAILSAFE_EXPIRATION_SECONDS constant value, for flexibility to adjust the timeout with longer waits if needed it.

The goal is to maintain flexibility to adjust the timeouts as needed, depending on the type of testing.

Copy link
Contributor Author

@juandediosg juandediosg left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

New changes have been made and are ready for review.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

TC-CGEN-2.2: Automate
3 participants