[HW]: Add mem_multibanked_pwrgate for correct power management #336
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (15)
src/mem_multibank_pwrgate.sv|22 col 101| Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|23 col 101| Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|24 col 101| Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|25 col 101| Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|26 col 101| Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|27 col 101| Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|28 col 28| Explicitly define a storage type for every parameter and localparam, (SimInit). [Style: constants] [explicit-parameter-storage-type]
src/mem_multibank_pwrgate.sv|28 col 101| Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|29 col 101| Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|30 col 28| Explicitly define a storage type for every parameter and localparam, (ImplKey). [Style: constants] [explicit-parameter-storage-type]
src/mem_multibank_pwrgate.sv|30 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|135 col 19| Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
src/mem_multibank_pwrgate.sv|138 col 22| Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
src/mem_multibank_pwrgate.sv|148 col 66| All generate block statements must have a label [Style: generate-statements] [generate-label]
src/mem_multibank_pwrgate.sv|153 col 101| Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 22 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L22
Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:22 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 23 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L23
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:23 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 24 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L24
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:24 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 25 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L25
Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:25 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 26 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L26
Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:26 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 27 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L27
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:27 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 28 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L28
Explicitly define a storage type for every parameter and localparam, (SimInit). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (SimInit). [Style: constants] [explicit-parameter-storage-type]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:28 column:28}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 28 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L28
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:28 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 29 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L29
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:29 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 30 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L30
Explicitly define a storage type for every parameter and localparam, (ImplKey). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (ImplKey). [Style: constants] [explicit-parameter-storage-type]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:30 column:28}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 30 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L30
Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:30 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 135 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L135
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
Raw output
message:"Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:135 column:19}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 138 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L138
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
Raw output
message:"Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:138 column:22}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 148 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L148
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:148 column:66}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 153 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L153
Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:153 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}