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src: Upstream latest modifications to Kairos chip
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@alex96295
alex96295 committed Feb 5, 2025
1 parent 84f0252 commit e1ae645
Showing 1 changed file with 149 additions and 29 deletions.
178 changes: 149 additions & 29 deletions src/dumpling/Chips/Kairos.py
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Original file line number Diff line number Diff line change
Expand Up @@ -137,6 +137,15 @@ def kairos(ctx, port_name, wtb_name, device_cycle_name, output):
help="Don't reset the chip before executing the binary. Helpfull for debugging and to keep custom config preloaded via "
"JTAG.",
)

@click.option(
"--no-resume",
is_flag=True,
default=False,
show_default=True,
help="Don't resume the core."
)

@pass_VectorWriter
def execute_elf(
writer: HP93000VectorWriter,
Expand All @@ -146,6 +155,7 @@ def execute_elf(
verify,
compress,
no_reset,
no_resume
):
"""Generate vectors to load and execute the given elf binary.
Expand Down Expand Up @@ -225,28 +235,30 @@ def execute_elf(
)
vector_writer.write_vectors(vectors, compress=compress)

# Resume core
vectors = riscv_debug_tap.init_dmi() # Change JTAG IR to DMIACCESS
vectors += riscv_debug_tap.resume_harts_no_loop(FC_CORE_ID, wait_cycles=100)
vector_writer.write_vectors(vectors, compress=compress)
if not no_resume:
# Resume core
vectors = riscv_debug_tap.init_dmi() # Change JTAG IR to DMIACCESS
vectors += riscv_debug_tap.resume_harts(FC_CORE_ID,"Resuming core", retries=16)
# vectors += riscv_debug_tap.resume_harts_no_loop(FC_CORE_ID, wait_cycles=100)
vector_writer.write_vectors(vectors, compress=compress)

# Wait for end of computation by polling EOC register address
if return_code != None:
if eoc_wait_cycles <= 0:
vectors = riscv_debug_tap.wait_for_end_of_computation(
return_code, idle_vector_count=100, max_retries=10
)
else:
vectors = [
jtag_driver.jtag_idle_vector(
repeat=eoc_wait_cycles,
comment="Waiting for computation to finish before checking EOC register.",
# Wait for end of computation by polling EOC register address
if return_code != None:
if eoc_wait_cycles <= 0:
vectors = riscv_debug_tap.wait_for_end_of_computation(
return_code, idle_vector_count=100, max_retries=10
)
]
vectors += riscv_debug_tap.check_end_of_computation(
return_code, wait_cycles=5000
)
vector_writer.write_vectors(vectors, compress=compress)
else:
vectors = [
jtag_driver.jtag_idle_vector(
repeat=eoc_wait_cycles,
comment="Waiting for computation to finish before checking EOC register.",
)
]
vectors += riscv_debug_tap.check_end_of_computation(
return_code, wait_cycles=5000
)
vector_writer.write_vectors(vectors, compress=compress)


@kairos.command()
Expand Down Expand Up @@ -524,7 +536,7 @@ def reset_chip(vector_writer: HP93000VectorWriter, reset_cycles):
vectors += jtag_driver.jtag_idle_vectors(10)
vectors += riscv_debug_tap.init_dmi()
vectors += riscv_debug_tap.set_dmactive(True)
vectors += jtag_driver.jtag_idle_vectors(10)
vectors += jtag_driver.jtag_idle_vectors(100000)
writer.write_vectors(vectors)


Expand All @@ -535,7 +547,7 @@ def reset_chip(vector_writer: HP93000VectorWriter, reset_cycles):
help="Read programm counter and compare it with the expected value provided",
)
@click.option(
"--resume/--no-resume",
"--resume",
show_default=True,
default=False,
help="Resume the core after reading the program counter.",
Expand Down Expand Up @@ -599,6 +611,7 @@ def halt_core_verify_pc(
@kairos.command()
@click.option(
"--return-code",
"-r",
default=0,
type=click.IntRange(min=0, max=255),
show_default=True,
Expand All @@ -607,25 +620,44 @@ def halt_core_verify_pc(
@click.option(
"--wait-cycles",
"-w",
type=click.IntRange(min=1),
type=click.IntRange(min=-10),
default=6,
show_default=True,
help="The number of cycles to wait for the eoc_register read operation to complete.",
)
@click.option(
"--compress",
'-c',
is_flag=True,
default=False,
show_default=True,
help="Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value."
)
@pass_VectorWriter
def check_eoc(vector_writer, return_code, wait_cycles):
def check_eoc(vector_writer, return_code, wait_cycles, compress):
"""Generate vectors to check for the end of computation.
Programs compiled with the pulp-sdk or pulp-runtime write their exit code to a special end-of-computation register
in APB SOC Control when they leave main. The expected return code (by default 0) can be modified to assume any value
between 0 and 255."""

# Wait for end of computation by polling EOC register address
with vector_writer as writer:
vectors = riscv_debug_tap.init_dmi()
vectors += riscv_debug_tap.check_end_of_computation(
return_code, wait_cycles=wait_cycles
)
writer.write_vectors(vectors)
if return_code != None:
if wait_cycles <= 0:
print("We are polling!")
vectors = riscv_debug_tap.wait_for_end_of_computation(return_code, idle_vector_count=500, max_retries=3000)
else:
vectors = [jtag_driver.jtag_idle_vector(repeat=wait_cycles, comment="Waiting for computation to finish before checking EOC register.")]
vectors += riscv_debug_tap.check_end_of_computation(return_code, wait_cycles=5000)
vector_writer.write_vectors(vectors, compress=compress)

#with vector_writer as writer:
# vectors = riscv_debug_tap.init_dmi()
# vectors += riscv_debug_tap.check_end_of_computation(
# return_code, wait_cycles=wait_cycles
# )
# writer.write_vectors(vectors)


@kairos.command()
Expand All @@ -639,3 +671,91 @@ def verify_idcode(vector_writer):
with vector_writer as writer:
vectors = riscv_debug_tap.verify_idcode()
writer.write_vectors(vectors)

@kairos.command()
@click.argument("FREQ", type=click.IntRange(min=0, max=1000000000000))
#@click.argument("FREQ", type=click.IntRange(min=1, max=1000))
@click.option("--fll", default='SOC_FLL', type=click.Choice(['CLU_FLL','PER_FLL', 'SOC_FLL']))
@click.option("--mult", default = '10', type=click.IntRange(min=1, max=65535))
@click.option("--clk-div", default='4', type=click.Choice(['1','2','4','8','16','32','64','128','256']), help="Change the clock division factor of DCO clock to FLL output clock.")
@click.option("--lock", '-l', is_flag = True, default=True, show_default=True, help="Gate the output clock with the FLL lock signal")
@click.option("--tolerance", default=80, show_default=True, type=click.IntRange(min=0, max=2047), help="The margin around the target multiplication factor for clock to be considered stable.")
@click.option("--stable-cycles", default=6, show_default=True, type=click.IntRange(min=0, max=63), help="The number of stable cycles unil LOCK is asserted.")
@click.option("--unstable-cycles", default=16, show_default=True, type=click.IntRange(min=0, max=63), help="The number of unstable cycles unil LOCK is de-asserted.")
@click.option("--enable-dithering", is_flag=True, default=False, show_default=True, help="Enable dithering for higher frequency resolution.")
@click.option("--loop-gain-exponent", default=-8, type=click.IntRange(min=-15,max=0), show_default=True, help="The gain exponent of the feedback loop. Gain = 2^<value>")
@click.option('--wait-cycles','-w', type=click.IntRange(min=1), default=200, show_default=True, help="The number of jtag cycles to wait between writing the two FLL config registers.")
@click.option("--pulp/--riscv", default=False, help="If true, the RISC-V TAP is used.")
@pass_VectorWriter
def change_freq(vector_writer: HP93000VectorWriter, freq, fll, mult, clk_div, lock, tolerance, stable_cycles, unstable_cycles, loop_gain_exponent, enable_dithering, wait_cycles, pulp):
""" Generate vectors to change the multiplication factor (MULT) and various other settings of the internal FLLs .
The FLL argument determines which of the two independent FLLs in Kairos is configured.
The output frequency of the FLL is freq =<ref_freq>*<MULT>/<clk-div>.
Since we need to write to two registers, we have to wait long enough for the FLL to become stable again before we try to modify the second registers.
"""

magic_address = BitArray('0x1c040000')

#print(len(magic_address))

if fll == "SOC_FLL":
config1_address = BitArray('0x1a100004')
config2_address = BitArray('0x1a100008')
config3_address = BitArray('0x1a10000c')
elif fll == "PER_FLL":
config1_address = BitArray('0x1a100014')
config2_address = BitArray('0x1a100018')
else:
config1_address = BitArray('0x1a100024')
config2_address = BitArray('0x1a100028')
clk_div_value = int(math.log2(int(clk_div)))+1
config1_value = bitstring.pack('0b1, bool, uint:4, uint:10=344, uint:16', lock, clk_div_value, mult)

freq_value = bitstring.pack('uint:32', freq)

# print("mult: %x" % mult)
# print("config1_value:", config1_value.hex)

print('freq:', freq)

config2_value = bitstring.pack('bool, 0b000, uint:12, uint:6, uint:6, uint:4',
enable_dithering,
tolerance,
stable_cycles, unstable_cycles, -loop_gain_exponent)

config3_value = bitstring.pack('uint:6=0, uint:10=322, uint:16=0')

with vector_writer as writer:
if pulp:
# Init pulp tap
vectors = pulp_tap.init_pulp_tap()
# Set FLL registers
#vectors += pulp_tap.write32(start_addr=config1_address, data=[config1_value], comment="[PULP_TAP] Configure {}".format(fll))
#vectors += [jtag_driver.jtag_idle_vector(repeat=wait_cycles)]
#vectors += pulp_tap.write32(start_addr=config2_address, data=[config2_value], comment="[PULP_TAP] Configure {}".format(fll))
vectors += pulp_tap.write32(start_addr=magic_address, data=[freq_value], comment="[PULP_TAP] Configure {}".format(fll))

vectors += [jtag_driver.jtag_idle_vector(repeat=wait_cycles)]
else:
# Init riscv debug module
vectors = riscv_debug_tap.init_dmi()
vectors += riscv_debug_tap.set_sbcs(True)
# Set FLL registers
# vectors += riscv_debug_tap.writeMem(addr=config2_address, data=config2_value, comment="[RISCV_DBG] Configure {}".format(fll))

#vectors += riscv_debug_tap.writeMem(addr=config3_address, data=config3_value, comment="[RISCV_DBG] Configure {}".format(fll))

#vectors += riscv_debug_tap.readMem(addr=config1_address, expected_data=config3_value, comment='')

#vectors += [jtag_driver.jtag_idle_vector(repeat=50)]

#vectors += riscv_debug_tap.writeMem(addr=config1_address, data=config1_value, comment="[RISCV_DBG] Configure {}".format(fll))
vectors += riscv_debug_tap.writeMem(addr=magic_address, data=freq_value, comment="[RISCV_DBG] Configure {}".format(fll))

vectors += [jtag_driver.jtag_idle_vector(repeat=wait_cycles)]

writer.write_vectors(vectors)

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