smmu: typo while port declaration

src/frontend/reg/tpl/idma_reg.sv.tpl

@@ -33,16 +33,16 @@ module idma_${identifier} #(
   input  reg_req_t [NumRegs-1:0] dma_ctrl_req_i,
   output reg_rsp_t [NumRegs-1:0] dma_ctrl_rsp_o,
   /// Request signals
-  output dma_req_t   dma_req_o,
-  output logic       req_valid_o,
-  input  logic       req_ready_i,
-  input  cnt_width_t next_id_i,
-  output stream_t    stream_idx_o,
-  output logic       smmu_f_bare,
-  output logic       smmu_f_exe,
-  output logic       smmu_f_user,
-  output logic       smmu_f_update_tlb,
-  output logic       smmu_pt_root_adr,
+  output dma_req_t    dma_req_o,
+  output logic        req_valid_o,
+  input  logic        req_ready_i,
+  input  cnt_width_t  next_id_i,
+  output stream_t     stream_idx_o,
+  output logic        smmu_f_bare,
+  output logic        smmu_f_exe,
+  output logic        smmu_f_user,
+  output logic        smmu_f_update_tlb,
+  output logic [63:0] smmu_pt_root_adr,
   /// Status signals
   input  cnt_width_t           [NumStreams-1:0] done_id_i,
   input  idma_pkg::idma_busy_t [NumStreams-1:0] busy_i,