VCS builds again

.gitlab-ci.yml

@@ -23,6 +23,6 @@ idma:
   needs: init
   trigger:
     include:
-      - artifact: nonfree/ci.yml
+      - artifact: nonfree/ci/ci.yml
         job: init
     strategy: depend

idma.mk

@@ -387,11 +387,11 @@ idma_nuke: idma_clean idma_nonfree_clean
 ## Phony Targets
 ## --------------
 
-.PHONY: idma_rtl_all idma_doc_all idma_sw_all
+.PHONY: idma_rtl_all idma_doc_all idma_sim_all
 
 idma_rtl_all: $(IDMA_RTL_ALL)
 
-idma_sw_all: help
+idma_sim_all: $(IDMA_VCS_DIR)/compile.sh $(IDMA_VSIM_DIR)/compile.tcl
 
 idma_doc_all: idma_spinx_doc
 

src/backend/idma_channel_coupler.sv

@@ -98,7 +98,7 @@ module idma_channel_coupler #(
     assign first = r_rsp_valid_i & r_rsp_ready_i & r_rsp_first_i & !r_decouple_aw_i;
 
     // stream fifo to hold AWs back
-    idma_stream_fifo #(
+    stream_fifo_optimal_wrap #(
         .Depth        ( NumAxInFlight ),
         .type_t       ( aw_ext_t      ),
         .PrintInfo    ( PrintFifoInfo )

src/backend/tpl/idma_backend.sv.tpl

@@ -570,7 +570,7 @@ _rsp_t ${protocol}_write_rsp_i,
     //--------------------------------------
     // Datapath decoupling
     //--------------------------------------
-    idma_stream_fifo #(
+    stream_fifo_optimal_wrap #(
         .Depth     ( NumAxInFlight ),
         .type_t    ( r_dp_req_t    ),
         .PrintInfo ( PrintFifoInfo )
@@ -588,7 +588,7 @@ _rsp_t ${protocol}_write_rsp_i,
         .ready_i    ( r_dp_req_out_ready  )
     );
 
-    idma_stream_fifo #(
+    stream_fifo_optimal_wrap #(
         .Depth     ( NumAxInFlight ),
         .type_t    ( w_dp_req_t    ),
         .PrintInfo ( PrintFifoInfo )
@@ -646,7 +646,7 @@ _rsp_t ${protocol}_write_rsp_i,
     //--------------------------------------
     // Last flag store
     //--------------------------------------
-    idma_stream_fifo #(
+    stream_fifo_optimal_wrap #(
         .Depth        ( MetaFifoDepth ),
         .type_t       ( logic [1:0]   ),
         .PrintInfo    ( PrintFifoInfo )

src/db/idma_axi.yml

@@ -8,6 +8,7 @@
 prefix: "axi"
 protocol_enum: "AXI"
 full_name: "AXI4+ATOP"
+tb_define: "PROT_AXI4"
 bursts: "split_at_page_boundary"
 page_size: 4096
 max_beats_per_burst: 256

src/db/idma_axi_lite.yml

@@ -8,6 +8,7 @@
 prefix: "axil"
 protocol_enum: "AXI_LITE"
 full_name: "AXI-Lite"
+tb_define: "PROT_AXI4_LITE"
 bursts: "not_supported"
 legalizer_force_decouple: "false"
 read_meta_channel: "ar_chan"

src/db/idma_axi_stream.yml

@@ -8,6 +8,7 @@
 prefix: "axis"
 protocol_enum: "AXI_STREAM"
 full_name: "AXI Stream"
+tb_define: "PROT_AXI4_STREAM"
 bursts: "not_supported"
 legalizer_force_decouple: "false"
 write_meta_channel: "t_chan"

src/db/idma_init.yml

@@ -8,6 +8,7 @@
 prefix: "init"
 protocol_enum: "INIT"
 full_name: "Memory Init"
+tb_define: "PROT_INIT"
 bursts: "not_supported"
 legalizer_force_decouple: "false"
 read_meta_channel: "req_chan"

src/db/idma_obi.yml

@@ -8,6 +8,7 @@
 prefix: "obi"
 protocol_enum: "OBI"
 full_name: "OBI"
+tb_define: "PROT_OBI"
 bursts: "not_supported"
 legalizer_force_decouple: "false"
 read_meta_channel: "a_chan"

src/db/idma_tilelink.yml

@@ -8,6 +8,7 @@
 prefix: "tilelink"
 protocol_enum: "TILELINK"
 full_name: "TileLink-UH"
+tb_define: "PROT_TILELINK"
 bursts: "only_pow2"
 page_size: 2048                # limited by TLToAXI4 Bridge -> To be AXI compliant -> Less than 256 beats
 tltoaxi4_compatibility_mode: "true" # If this is true burst will never cross a page boundary and only 32 beat write bursts -> Needed for TLToAXI4 Bridge

test/include/tb_tasks.svh

@@ -7,6 +7,7 @@
 
 
     // write a byte to the AXI-attached memory
+`ifdef PROT_AXI
     task write_byte_axi_mem (
         input byte_t byte_i,
         input addr_t addr_i
@@ -24,7 +25,25 @@
         else
             byte_o = '1;
     endtask
+`else
+    task write_byte_axi_mem (
+        input byte_t byte_i,
+        input addr_t addr_i
+    );
+        $fatal(1, "AXI Protocol not available");
+    endtask
+
+    // read a byte from the AXI-attached memory
+    task read_byte_axi_mem (
+        output byte_t byte_o,
+        input  addr_t addr_i
+    );
+        $fatal(1, "AXI Protocol not available");
+        byte_o = 'x;
+    endtask
+`endif
 
+`ifdef PROT_AXI_LITE
     // write a byte to the AXI-Lite AXI-attached memory
     task write_byte_axi_lite_axi_mem (
         input byte_t byte_i,
@@ -43,7 +62,26 @@
         else
             byte_o = '1;
     endtask
+`else
+    // write a byte to the AXI-Lite AXI-attached memory
+    task write_byte_axi_lite_axi_mem (
+        input byte_t byte_i,
+        input addr_t addr_i
+    );
+        $fatal(1, "AXI Lite Protocol not available");
+    endtask
 
+    // read a byte from the AXI-Lite AXI-attached memory
+    task read_byte_axi_lite_axi_mem (
+        output byte_t byte_o,
+        input  addr_t addr_i
+    );
+        $fatal(1, "AXI Lite Protocol not available");
+        byte_o = 'x;
+    endtask
+`endif
+
+`ifdef PROT_OBI
     // write a byte to the OBI AXI-attached memory
     task write_byte_obi_axi_mem (
         input byte_t byte_i,
@@ -62,7 +100,26 @@
         else
             byte_o = '1;
     endtask
+`else
+    // write a byte to the OBI AXI-attached memory
+    task write_byte_obi_axi_mem (
+        input byte_t byte_i,
+        input addr_t addr_i
+    );
+        $fatal(1, "OBI Protocol not available");
+    endtask
+
+    // read a byte from the OBI AXI-attached memory
+    task read_byte_obi_axi_mem (
+        output byte_t byte_o,
+        input  addr_t addr_i
+    );
+        $fatal(1, "OBI Protocol not available");
+        byte_o = 'x;
+    endtask
+`endif
 
+`ifdef PROT_TILELINK
     // write a byte to the TileLink AXI-attached memory
     task write_byte_tilelink_axi_mem (
         input byte_t byte_i,
@@ -81,7 +138,26 @@
         else
             byte_o = '1;
     endtask
+`else
+    // write a byte to the TileLink AXI-attached memory
+    task write_byte_tilelink_axi_mem (
+        input byte_t byte_i,
+        input addr_t addr_i
+    );
+        $fatal(1, "TileLink Protocol not available");
+    endtask
 
+    // read a byte from the TileLink AXI-attached memory
+    task read_byte_tilelink_axi_mem (
+        output byte_t byte_o,
+        input  addr_t addr_i
+    );
+        $fatal(1, "TileLink Protocol not available");
+        byte_o = 'x;
+    endtask
+`endif
+
+`ifdef PROT_AXI_STREAM
     // write a byte to the AXI Stream AXI-attached memory
     task write_byte_axi_stream_axi_mem (
         input byte_t byte_i,
@@ -100,7 +176,26 @@
         else
             byte_o = '1;
     endtask
+`else
+    // write a byte to the AXI Stream AXI-attached memory
+    task write_byte_axi_stream_axi_mem (
+        input byte_t byte_i,
+        input addr_t addr_i
+    );
+        $fatal(1, "AXI Stream Protocol not available");
+    endtask
 
+    // read a byte from the AXI Stream AXI-attached memory
+    task read_byte_axi_stream_axi_mem (
+        output byte_t byte_o,
+        input  addr_t addr_i
+    );
+        $fatal(1, "AXI Stream Protocol not available");
+        byte_o = 'x;
+    endtask
+`endif
+
+`ifdef PROT_AXI
     // set error flag in the AXI-attached memory
     task set_error_mem (
         input addr_t          addr_i,
@@ -112,6 +207,16 @@
         else
             i_axi_sim_mem.werr[addr_i] = resp_i;
     endtask
+`else
+     // set error flag in the AXI-attached memory
+    task set_error_mem (
+        input addr_t          addr_i,
+        input logic           is_read_i,
+        input axi_pkg::resp_t resp_i
+    );
+        $fatal(1, "AXI Protocol not available");
+    endtask
+`endif
 
     // compare if a range of bytes matches
     task compare_mem (

test/tpl/tb_idma_backend.sv.tpl

@@ -9,6 +9,8 @@
 `include "axi/typedef.svh"
 `include "idma/typedef.svh"
 
+// Protocol testbench defines
+${tb_defines}
 module tb_idma_backend_${name_uniqueifier} import idma_pkg::*; #(
     parameter int unsigned BufferDepth           = 3,
     parameter int unsigned NumAxInFlight         = 3,

util/mario/testbench.py

@@ -23,6 +23,7 @@ def render_testbench(prot_ids: dict, db: dict, tpl_file: str) -> str:
 
         read_bridges = {}
         write_bridges = {}
+        tb_defines = ''
 
         # iterate over the protocols in use
         for up in prot_ids[prot_id]['used']:
@@ -39,6 +40,9 @@ def render_testbench(prot_ids: dict, db: dict, tpl_file: str) -> str:
                     db[up]['read_bridge_template'] =\
                         '    ' + db[up]['read_bridge_template'].replace('\n', '\n    ')
 
+            # assemble tb_defines
+            tb_defines += f'`define {db[up]["tb_define"]}\n'
+
         # iterate over the protocols in use
         for rp in prot_ids[prot_id]['ar']:
 
@@ -86,7 +90,8 @@ def render_testbench(prot_ids: dict, db: dict, tpl_file: str) -> str:
             'one_read_port': len(prot_ids[prot_id]['ar']) == 1,
             'one_write_port': len(prot_ids[prot_id]['aw']) == 1,
             'rendered_read_bridges': read_bridges,
-            'rendered_write_bridges': write_bridges
+            'rendered_write_bridges': write_bridges,
+            'tb_defines': tb_defines
         }
 
         # render