verilog port direction

"A continuous assignment is implied when a variable is connected to an input port declaration. This makes assignments to a variable declared as an input port illegal. A continuous assignment is implied when a variable is connected to the output port of an instance. This makes procedural or continuous assignments to a variable connected to the output port of an instance illegal."

EDIT: This tongue twister implies the following:

class Top():
  def __init__( s ):
    s.ctrl = Ctrl()
    
    @s.update
    def up_illegal():
      s.ctrl.out = 123

class Ctrl():
  def __init__( s ):
    s.in_ = InVPort(...)
    s.out = OutVPort(...)
    
    @s.update
    def up_ctrl_illegal():
      s.in_ = 123

top = Top()

"This makes assignments to a variable declared as an input port illegal":

• It is illegal if up_ctrl_illegal in top.ctrl writes s.in_ (which is essentially top.ctrl.in).

"This makes procedural or continuous assignments to a variable connected to the output port of an instance illegal."

• It is illegal if up_illegal in top writes s.ctrl.out