sync: make it 8ns long

dac_data.py

@@ -37,14 +37,14 @@ def __init__(self, pins, swap=((0, 3), (1, 8))):
         ]
 
         i = Signal(max=4, reset_less=True)
-        sync = Signal(8, reset_less=True)
+        sync = Signal(12, reset_less=True)
 
         self.sync += [
             i.eq(i + 1),
-            sync.eq(sync[4:]),
+            sync.eq(sync[2:]),
             If(self.data_sync,
                 i.eq(0),
-                sync.eq(1 << self.sync_dly),
+                sync.eq(0xf << self.sync_dly),
             ),
             self.istr.eq(0),
             If(i == 4 - 1,
@@ -59,7 +59,7 @@ def __init__(self, pins, swap=((0, 3), (1, 8))):
 
         # SYNC for PLL N divider which generates internal fifo write pointer
         # reset OSTR, timed to dac_clk!, not needed if N=1
-        self._oserdes(sync, pins.sync_p, pins.sync_n)
+        self._oserdes([sync[0], sync[0], sync[1], sync[1]], pins.sync_p, pins.sync_n)
 
         # ISTR for write pointer
         self._oserdes([self.istr, 0, 0, 0],

decode.py

@@ -18,7 +18,7 @@
 # 0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef
 # ____----____----____----____----____----____----____----____----____----____----
 # 66666666666666666666666666666665666666656666666566666665666666656666666566666660
-#   4 2 0  4 2 0  4 2 0  4 2 0  4 
+#   4 2 0  4 2 0  4 2 0  4 2 0  4
 
 class SampleGearbox(Module):
     """Variable width input uneven ratio gearbox (e.g. 5/6 to 7)

example.py

@@ -26,8 +26,7 @@ def do(self):
     def inner(self):
         f = self.phaser0
 
-        delay(1*ms)
-        f.init()
+        f.init(debug=True)
 
         for ch in range(2):
             f.channel[ch].set_att(0*dB)
@@ -61,5 +60,5 @@ def inner(self):
         alarm = f.dac_read(0x05)
         self.p(alarm)
         self.core.break_realtime()
-        # f.set_cfg(dac_sleep=1, trf0_ps=1, trf1_ps=1)
+        f.set_cfg(dac_sleep=1, trf0_ps=1, trf1_ps=1)
         self.core.wait_until_mu(now_mu())