Add TIM4 implementation

src/gpio.rs

@@ -3,7 +3,7 @@ use core::marker::PhantomData;
 
 use paste::paste;
 
-use crate::pac::{EXTI, GPIOA, GPIOB, GPIOC};
+use crate::pac::{EXTI, GPIOA, GPIOB, GPIOC, GPIOD};
 use crate::rcc::{Rcc, ResetEnable};
 
 #[cfg(feature = "stm32g0b1")]
@@ -403,6 +403,26 @@ gpio!(GPIOC, pc, [
     PC15: (15, Analog, afrh, AF_B_H, exticr4, exti24_31),
 ]);
 
+gpio!(GPIOD, pd, [
+    // Pin: (pin, default_mode, bits...)
+    PD0:  (0,  Analog, afrl, AF_B_L, exticr1, exti0_7  ),
+    PD1:  (1,  Analog, afrl, AF_B_L, exticr1, exti8_15 ),
+    PD2:  (2,  Analog, afrl, AF_B_L, exticr1, exti16_23),
+    PD3:  (3,  Analog, afrl, AF_B_L, exticr1, exti24_31),
+    PD4:  (4,  Analog, afrl, AF_B_L, exticr2, exti0_7  ),
+    PD5:  (5,  Analog, afrl, AF_B_L, exticr2, exti8_15 ),
+    PD6:  (6,  Analog, afrl, AF_B_L, exticr2, exti16_23),
+    PD7:  (7,  Analog, afrl, AF_B_L, exticr2, exti24_31),
+    PD8:  (8,  Analog, afrh, AF_B_H, exticr3, exti0_7  ),
+    PD9:  (9,  Analog, afrh, AF_B_H, exticr3, exti8_15 ),
+    PD10: (10, Analog, afrh, AF_B_H, exticr3, exti16_23),
+    PD11: (11, Analog, afrh, AF_B_H, exticr3, exti24_31),
+    PD12: (12, Analog, afrh, AF_B_H, exticr4, exti0_7  ),
+    PD13: (13, Analog, afrh, AF_B_H, exticr4, exti8_15 ),
+    PD14: (14, Analog, afrh, AF_B_H, exticr4, exti16_23),
+    PD15: (15, Analog, afrh, AF_B_H, exticr4, exti24_31),
+]);
+
 // GPIOE can't be used as EXTI interrupt source
 #[cfg(feature = "stm32g0b1")]
 gpio!(GPIOE, pe, [

src/rcc/reset_enable.rs

@@ -4,7 +4,7 @@ use crate::pac::{
 };
 
 #[cfg(feature = "stm32g0b1")]
-use crate::pac::GPIOE;
+use crate::pac::{GPIOE, TIM4};
 
 use super::{Rcc, ResetEnable};
 
@@ -59,6 +59,8 @@ reset_enable!(DMA1, AHB, dma1en, dma1rst); // 0
 // APB1 devices
 reset_enable!(TIM2, APB1, tim2en, tim2rst); // 0
 reset_enable!(TIM3, APB1, tim3en, tim3rst); // 1
+#[cfg(feature = "stm32g0b1")]
+reset_enable!(TIM4, APB1, tim4en, tim4rst); // 2
 reset_enable!(I2C1, APB1, i2c1en, i2c1rst); // 21
 reset_enable!(I2C2, APB1, i2c2en, i2c2rst); // 22
 reset_enable!(LPTIM2, APB1, lptim2en, lptim2rst); // 30

src/timer/timers.rs

@@ -4,12 +4,15 @@ use core::marker::PhantomData;
 use crate::gpio::gpioa::*;
 use crate::gpio::gpiob::*;
 use crate::gpio::gpioc::*;
+use crate::gpio::gpiod::*;
 use crate::gpio::Alternate;
 use crate::pac::{TIM2, TIM3};
 use crate::rcc::{Rcc, ResetEnable};
 
 #[cfg(feature = "stm32g0b1")]
 use crate::gpio::gpioe::{PE3, PE4, PE5, PE6};
+#[cfg(feature = "stm32g0b1")]
+use crate::pac::TIM4;
 
 /// Wrapper for timer peripheral.
 #[derive(Debug)]
@@ -92,7 +95,11 @@ macro_rules! general_purpose_timer {
             }
 
             pub fn counter(&self) -> $REG {
-                self.timer.cnt().read().cnt().bits()
+                #[cfg(feature = "stm32g071")]
+                return self.timer.cnt().read().cnt().bits();
+                #[cfg(feature = "stm32g0b1")]
+                // TODO: for whatever reason 16-bit TIM4 is using 32-bit TIM2 register block.
+                return self.timer.cnt().read().cnt().bits() as $REG;
             }
         }
 
@@ -115,6 +122,8 @@ macro_rules! general_purpose_timer {
 
 general_purpose_timer!(TIM2, u32);
 general_purpose_timer!(TIM3, u16);
+#[cfg(feature = "stm32g0b1")]
+general_purpose_timer!(TIM4, u16);
 
 pub struct Channel1;
 pub struct Channel2;
@@ -247,3 +256,12 @@ pwm!(TIM3, [
         Channel4 => ccr4, cc4e, ccmr2_output, oc4m, oc4pe, [(PB1, 1), (PC9, 1), (PE6, 1),],
     ]
 );
+
+#[cfg(feature = "stm32g0b1")]
+pwm!(TIM4, [
+        Channel1 => ccr1, cc1e, ccmr1_output, oc1m, oc1pe, [(PB6, 9), (PD12, 2),],
+        Channel2 => ccr2, cc2e, ccmr1_output, oc2m, oc2pe, [(PB7, 9), (PD13, 2),],
+        Channel3 => ccr3, cc3e, ccmr2_output, oc3m, oc3pe, [(PB8, 9), (PD14, 2),],
+        Channel4 => ccr4, cc4e, ccmr2_output, oc4m, oc4pe, [(PB9, 9), (PD15, 2),],
+    ]
+);