Merge pull request #847 from rdaly525/update-tests-linebreaks

Update gold files for linebreaks

tests/binary/gold/concat.v

@@ -1,18 +1,56 @@
-module coreir_slice #(parameter hi = 1, parameter lo = 0, parameter width = 1) (input [width-1:0] in, output [hi-lo-1:0] out);
+module coreir_slice #(
+    parameter hi = 1,
+    parameter lo = 0,
+    parameter width = 1
+) (
+    input [width-1:0] in,
+    output [hi-lo-1:0] out
+);
   assign out = in[hi-1:lo];
 endmodule
 
-module coreir_concat #(parameter width0 = 1, parameter width1 = 1) (input [width0-1:0] in0, input [width1-1:0] in1, output [width0+width1-1:0] out);
+module coreir_concat #(
+    parameter width0 = 1,
+    parameter width1 = 1
+) (
+    input [width0-1:0] in0,
+    input [width1-1:0] in1,
+    output [width0+width1-1:0] out
+);
   assign out = {in1,in0};
 endmodule
 
-module concats (input [15:0] in, output [15:0] out);
+module concats (
+    input [15:0] in,
+    output [15:0] out
+);
 wire [15:0] cc0_out;
 wire [3:0] s0_out;
 wire [11:0] s1_out;
-coreir_concat #(.width0(4), .width1(12)) cc0(.in0(s0_out), .in1(s1_out), .out(cc0_out));
-coreir_slice #(.hi(16), .lo(12), .width(16)) s0(.in(in), .out(s0_out));
-coreir_slice #(.hi(15), .lo(3), .width(16)) s1(.in(in), .out(s1_out));
+coreir_concat #(
+    .width0(4),
+    .width1(12)
+) cc0 (
+    .in0(s0_out),
+    .in1(s1_out),
+    .out(cc0_out)
+);
+coreir_slice #(
+    .hi(16),
+    .lo(12),
+    .width(16)
+) s0 (
+    .in(in),
+    .out(s0_out)
+);
+coreir_slice #(
+    .hi(15),
+    .lo(3),
+    .width(16)
+) s1 (
+    .in(in),
+    .out(s1_out)
+);
 assign out = cc0_out;
 endmodule
 

tests/gtest/add_golden.v

@@ -1,4 +1,8 @@
-module Top (input [7:0] I0, input [7:0] I1, output [7:0] O);
+module Top (
+    input [7:0] I0,
+    input [7:0] I1,
+    output [7:0] O
+);
 assign O = I0 + I1;
 endmodule
 

tests/gtest/array_select_golden.v

@@ -2,11 +2,20 @@
 module foo (input [3:0] I, output [3:0] O);
     assign O = I;
 endmodule
-module top (input [3:0] self_I, output [3:0] O);
+module top (
+    input [3:0] self_I,
+    output [3:0] O
+);
 wire [3:0] inst0_O;
 wire [3:0] inst1_O;
-foo inst0(.I({self_I[2],self_I[1],self_I[0],self_I[0]}), .O(inst0_O));
-foo inst1(.I({self_I[1],inst0_O[1],inst0_O[1],inst0_O[0]}), .O(inst1_O));
+foo inst0 (
+    .I({self_I[2],self_I[1],self_I[0],self_I[0]}),
+    .O(inst0_O)
+);
+foo inst1 (
+    .I({self_I[1],inst0_O[1],inst0_O[1],inst0_O[0]}),
+    .O(inst1_O)
+);
 assign O = {self_I[1],self_I[0],inst1_O[0],inst1_O[0]};
 endmodule
 

tests/gtest/blackbox_verilog_golden.v

@@ -2,7 +2,13 @@
 module foo (input I, output O);
     assign O = I;
 endmodule
-module top (input I, output O);
-foo inst0(.I(I), .O(O));
+module top (
+    input I,
+    output O
+);
+foo inst0 (
+    .I(I),
+    .O(O)
+);
 endmodule
 

tests/gtest/debug_info_golden.v

@@ -1,6 +1,10 @@
 // Module `Term2` defined externally
 // Module `And2` defined externally
-module main (input [1:0] I, output O, output [1:0] O1);
+module main (
+    input [1:0] I,
+    output O,
+    output [1:0] O1
+);
 // Module `main` defined at tests/test_circuit/test_define.py:57
 wire and2_0_O;
 wire and2_1_O;
@@ -9,23 +13,41 @@ wire and2_3_O;
 // Instance `and2_0` created at tests/test_circuit/test_define.py:61
 // Connection `(and2_0.I0, I[0])` created at tests/test_circuit/test_define.py:63
 // Connection `(and2_0.I1, I[1])` created at tests/test_circuit/test_define.py:64
-And2 and2_0(.I0(I[0]), .I1(I[1]), .O(and2_0_O));
+And2 and2_0 (
+    .I0(I[0]),
+    .I1(I[1]),
+    .O(and2_0_O)
+);
 // Instance `and2_1` created at tests/test_circuit/test_define.py:61
 // Connection `(and2_1.I0, and2_0_O)` created at tests/test_circuit/test_define.py:66
 // Connection `(and2_1.I1, I[1])` created at tests/test_circuit/test_define.py:67
-And2 and2_1(.I0(and2_0_O), .I1(I[1]), .O(and2_1_O));
+And2 and2_1 (
+    .I0(and2_0_O),
+    .I1(I[1]),
+    .O(and2_1_O)
+);
 // Instance `and2_2` created at tests/test_circuit/test_define.py:61
 // Connection `(and2_2.I0, and2_1_O)` created at tests/test_circuit/test_define.py:66
 // Connection `(and2_2.I1, I[1])` created at tests/test_circuit/test_define.py:67
-And2 and2_2(.I0(and2_1_O), .I1(I[1]), .O(and2_2_O));
+And2 and2_2 (
+    .I0(and2_1_O),
+    .I1(I[1]),
+    .O(and2_2_O)
+);
 // Instance `and2_3` created at tests/test_circuit/test_define.py:61
 // Connection `(and2_3.I0, and2_2_O)` created at tests/test_circuit/test_define.py:66
 // Connection `(and2_3.I1, I[1])` created at tests/test_circuit/test_define.py:67
-And2 and2_3(.I0(and2_2_O), .I1(I[1]), .O(and2_3_O));
+And2 and2_3 (
+    .I0(and2_2_O),
+    .I1(I[1]),
+    .O(and2_3_O)
+);
 // Instance `term0` created at tests/test_circuit/test_define.py:77
 // Connection `(term0.I[1], and2_2_O)` created at tests/test_circuit/test_define.py:103
 // Connection `(term0.I[0], and2_3_O)` created at tests/test_circuit/test_define.py:99
-Term2 term0(.I({and2_2_O,and2_3_O}));
+Term2 term0 (
+    .I({and2_2_O,and2_3_O})
+);
 // Connection `(O, and2_3_O)` created at tests/test_circuit/test_define.py:70
 assign O = and2_3_O;
 // Connection `(O1[0], and2_2_O)` created at tests/test_circuit/test_define.py:77

tests/gtest/inline_verilog_golden.v

@@ -3,8 +3,16 @@ always @(posedge CLK) begin
   O <= I;
 end
 endmodule
-module Main (input I, output O, input CLK);
-FF FF_inst0(.I(I), .O(O), .CLK(CLK));
+module Main (
+    input I,
+    output O,
+    input CLK
+);
+FF FF_inst0 (
+    .I(I),
+    .O(O),
+    .CLK(CLK)
+);
 
 assert property { @(posedge CLK) I |-> ##1 O };
 

tests/gtest/inline_verilog_top_golden.v

@@ -1,4 +1,21 @@
-module Monitor (input CLK, input handshake_arr_0_ready, input handshake_arr_0_valid, input handshake_arr_1_ready, input handshake_arr_1_valid, input handshake_arr_2_ready, input handshake_arr_2_valid, input handshake_ready, input handshake_valid, input [3:0] in1, input [3:0] in2, input intermediate_tuple__0, input intermediate_tuple__1, input mon_temp1, input mon_temp2, input out);
+module Monitor (
+    input CLK,
+    input handshake_arr_0_ready,
+    input handshake_arr_0_valid,
+    input handshake_arr_1_ready,
+    input handshake_arr_1_valid,
+    input handshake_arr_2_ready,
+    input handshake_arr_2_valid,
+    input handshake_ready,
+    input handshake_valid,
+    input [3:0] in1,
+    input [3:0] in2,
+    input intermediate_tuple__0,
+    input intermediate_tuple__1,
+    input mon_temp1,
+    input mon_temp2,
+    input out
+);
 
                         logic temp1, temp2;
                         assign temp1 = |(in1);

tests/gtest/intermediate_connection_golden.v

@@ -3,12 +3,25 @@ module foo (input I, inout IO, output O);
     assign O = I;
     assign IO = I;
 endmodule
-module top (input I, inout IO0, inout IO1, output O);
+module top (
+    input I,
+    inout IO0,
+    inout IO1,
+    output O
+);
 wire inst0_IO;
 wire inst0_O;
 wire inst1_IO;
-foo inst0(.I(I), .IO(inst0_IO), .O(inst0_O));
-foo inst1(.I(inst0_O), .IO(inst1_IO), .O(O));
+foo inst0 (
+    .I(I),
+    .IO(inst0_IO),
+    .O(inst0_O)
+);
+foo inst1 (
+    .I(inst0_O),
+    .IO(inst1_IO),
+    .O(O)
+);
 assign inst0_IO = inst1_IO;
 assign IO0 = inst0_IO;
 assign inst0_IO = IO1;

tests/gtest/mux_golden.v

@@ -1,24 +1,93 @@
-module commonlib_muxn__N2__width8 (input [7:0] in_data_0, input [7:0] in_data_1, input [0:0] in_sel, output [7:0] out);
+module commonlib_muxn__N2__width8 (
+    input [7:0] in_data_0,
+    input [7:0] in_data_1,
+    input [0:0] in_sel,
+    output [7:0] out
+);
 assign out = in_sel[0] ? in_data_1 : in_data_0;
 endmodule
 
-module commonlib_muxn__N4__width8 (input [7:0] in_data_0, input [7:0] in_data_1, input [7:0] in_data_2, input [7:0] in_data_3, input [1:0] in_sel, output [7:0] out);
+module commonlib_muxn__N4__width8 (
+    input [7:0] in_data_0,
+    input [7:0] in_data_1,
+    input [7:0] in_data_2,
+    input [7:0] in_data_3,
+    input [1:0] in_sel,
+    output [7:0] out
+);
 wire [7:0] muxN_0_out;
 wire [7:0] muxN_1_out;
-commonlib_muxn__N2__width8 muxN_0(.in_data_0(in_data_0), .in_data_1(in_data_1), .in_sel(in_sel[1 - 1:0]), .out(muxN_0_out));
-commonlib_muxn__N2__width8 muxN_1(.in_data_0(in_data_2), .in_data_1(in_data_3), .in_sel(in_sel[1 - 1:0]), .out(muxN_1_out));
+commonlib_muxn__N2__width8 muxN_0 (
+    .in_data_0(in_data_0),
+    .in_data_1(in_data_1),
+    .in_sel(in_sel[1 - 1:0]),
+    .out(muxN_0_out)
+);
+commonlib_muxn__N2__width8 muxN_1 (
+    .in_data_0(in_data_2),
+    .in_data_1(in_data_3),
+    .in_sel(in_sel[1 - 1:0]),
+    .out(muxN_1_out)
+);
 assign out = in_sel[1] ? muxN_1_out : muxN_0_out;
 endmodule
 
-module commonlib_muxn__N8__width8 (input [7:0] in_data_0, input [7:0] in_data_1, input [7:0] in_data_2, input [7:0] in_data_3, input [7:0] in_data_4, input [7:0] in_data_5, input [7:0] in_data_6, input [7:0] in_data_7, input [2:0] in_sel, output [7:0] out);
+module commonlib_muxn__N8__width8 (
+    input [7:0] in_data_0,
+    input [7:0] in_data_1,
+    input [7:0] in_data_2,
+    input [7:0] in_data_3,
+    input [7:0] in_data_4,
+    input [7:0] in_data_5,
+    input [7:0] in_data_6,
+    input [7:0] in_data_7,
+    input [2:0] in_sel,
+    output [7:0] out
+);
 wire [7:0] muxN_0_out;
 wire [7:0] muxN_1_out;
-commonlib_muxn__N4__width8 muxN_0(.in_data_0(in_data_0), .in_data_1(in_data_1), .in_data_2(in_data_2), .in_data_3(in_data_3), .in_sel(in_sel[2 - 1:0]), .out(muxN_0_out));
-commonlib_muxn__N4__width8 muxN_1(.in_data_0(in_data_4), .in_data_1(in_data_5), .in_data_2(in_data_6), .in_data_3(in_data_7), .in_sel(in_sel[2 - 1:0]), .out(muxN_1_out));
+commonlib_muxn__N4__width8 muxN_0 (
+    .in_data_0(in_data_0),
+    .in_data_1(in_data_1),
+    .in_data_2(in_data_2),
+    .in_data_3(in_data_3),
+    .in_sel(in_sel[2 - 1:0]),
+    .out(muxN_0_out)
+);
+commonlib_muxn__N4__width8 muxN_1 (
+    .in_data_0(in_data_4),
+    .in_data_1(in_data_5),
+    .in_data_2(in_data_6),
+    .in_data_3(in_data_7),
+    .in_sel(in_sel[2 - 1:0]),
+    .out(muxN_1_out)
+);
 assign out = in_sel[2] ? muxN_1_out : muxN_0_out;
 endmodule
 
-module Mux8x8 (input [7:0] I0, input [7:0] I1, input [7:0] I2, input [7:0] I3, input [7:0] I4, input [7:0] I5, input [7:0] I6, input [7:0] I7, input [2:0] S, output [7:0] O);
-commonlib_muxn__N8__width8 coreir_commonlib_mux8x8_inst0(.in_data_0(I0), .in_data_1(I1), .in_data_2(I2), .in_data_3(I3), .in_data_4(I4), .in_data_5(I5), .in_data_6(I6), .in_data_7(I7), .in_sel(S), .out(O));
+module Mux8x8 (
+    input [7:0] I0,
+    input [7:0] I1,
+    input [7:0] I2,
+    input [7:0] I3,
+    input [7:0] I4,
+    input [7:0] I5,
+    input [7:0] I6,
+    input [7:0] I7,
+    input [2:0] S,
+    output [7:0] O
+);
+commonlib_muxn__N8__width8 coreir_commonlib_mux8x8_inst0 (
+    .in_data_0(I0),
+    .in_data_1(I1),
+    .in_data_2(I2),
+    .in_data_3(I3),
+    .in_data_4(I4),
+    .in_data_5(I5),
+    .in_data_6(I6),
+    .in_data_7(I7),
+    .in_sel(S),
+    .out(O)
+);
 endmodule
 

tests/gtest/port_order_golden.v

@@ -1,12 +1,34 @@
-module Add8_cin (input [7:0] z, input [7:0] x, output [7:0] a, input CIN);
+module Add8_cin (
+    input [7:0] z,
+    input [7:0] x,
+    output [7:0] a,
+    input CIN
+);
 assign a = (({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CIN}) + z) + x;
 endmodule
 
-module Sub8 (input [7:0] z, input [7:0] x, output [7:0] a);
-Add8_cin inst1(.z(z), .x(~ x), .a(a), .CIN(1'b1));
+module Sub8 (
+    input [7:0] z,
+    input [7:0] x,
+    output [7:0] a
+);
+Add8_cin inst1 (
+    .z(z),
+    .x(~ x),
+    .a(a),
+    .CIN(1'b1)
+);
 endmodule
 
-module test_two_ops (input [7:0] z, input [7:0] x, output [7:0] a);
-Sub8 inst1(.z(z + x), .x(z), .a(a));
+module test_two_ops (
+    input [7:0] z,
+    input [7:0] x,
+    output [7:0] a
+);
+Sub8 inst1 (
+    .z(z + x),
+    .x(z),
+    .a(a)
+);
 endmodule