Update gold

rdaly525 · Feb 21, 2020 · c2e56e7 · c2e56e7
1 parent 231c296
commit c2e56e7
Showing 1 changed file with 21 additions and 2 deletions.
diff --git a/tests/unit/gold/ice40_pll_verilog.v b/tests/unit/gold/ice40_pll_verilog.v
@@ -1,8 +1,27 @@
 // Module `SB_PLL40_CORE` defined externally
-module top (input clk, input reset, input in, output out, output outClk);
+module top (
+    input clk,
+    input reset,
+    input in,
+    output out,
+    output outClk
+);
 wire pll_PLLOUTCORE;
 wire pll_PLLOUTGLOBAL;
-SB_PLL40_CORE #(.DIVF(7'h21), .DIVQ(3'h4), .DIVR(4'h0), .FEEDBACK_PATH("SIMPLE"), .FILTER_RANGE(3'h1), .PLLOUT_SELECT("GENCLK")) pll(.BYPASS(in), .PLLOUTCORE(pll_PLLOUTCORE), .PLLOUTGLOBAL(pll_PLLOUTGLOBAL), .REFERENCECLK(clk), .RESETB(reset));
+SB_PLL40_CORE #(
+    .DIVF(7'h21),
+    .DIVQ(3'h4),
+    .DIVR(4'h0),
+    .FEEDBACK_PATH("SIMPLE"),
+    .FILTER_RANGE(3'h1),
+    .PLLOUT_SELECT("GENCLK")
+) pll (
+    .BYPASS(in),
+    .PLLOUTCORE(pll_PLLOUTCORE),
+    .PLLOUTGLOBAL(pll_PLLOUTGLOBAL),
+    .REFERENCECLK(clk),
+    .RESETB(reset)
+);
 assign out = pll_PLLOUTCORE;
 assign outClk = pll_PLLOUTGLOBAL;
 endmodule