Merge pull request #827 from rdaly525/hotfix-inline-corebit

Hotfix inline corebit
rdaly525 · Jan 13, 2020 · fb025bc · fb025bc
2 parents 5279e70 + 6cb5980
commit fb025bc
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Showing 4 changed files with 114 additions and 3 deletions.
diff --git a/src/passes/analysis/verilog.cpp b/src/passes/analysis/verilog.cpp
@@ -96,9 +96,25 @@ bool can_inline_binary_op(CoreIR::Module *module, bool _inline) {
              verilog_json["primitive_type"] == "binaryReduce")
             && _inline;
     }
+    if (module->getMetaData().count("verilog") > 0) {
+        json verilog_json =
+            module->getMetaData()["verilog"];
+        return module->hasPrimitiveExpressionLambda() &&
+            (verilog_json["primitive_type"] == "binary" ||
+             verilog_json["primitive_type"] == "binaryReduce")
+            && _inline;
+    }
     return false;
 }
 
+std::unique_ptr<vAST::Expression> get_primitive_expr(CoreIR::Instance *instance) {
+    CoreIR::Module *module = instance->getModuleRef();
+    if (module->isGenerated()) {
+        return module->getGenerator()->getPrimitiveExpressionLambda()();
+    }
+    return module->getPrimitiveExpressionLambda()();
+}
+
 std::unique_ptr<vAST::StructuralStatement> inline_binary_op(
     std::pair<std::string, CoreIR::Instance *> instance,
     std::map<std::string, std::unique_ptr<vAST::Expression>> verilog_connections
@@ -108,7 +124,7 @@ std::unique_ptr<vAST::StructuralStatement> inline_binary_op(
             std::move(verilog_connections["in1"]));
     return std::make_unique<vAST::ContinuousAssign>(
         std::make_unique<vAST::Identifier>(instance.first + "_out"),
-        transformer.visit(instance.second->getModuleRef()->getGenerator()->getPrimitiveExpressionLambda()()));
+        transformer.visit(get_primitive_expr(instance.second)));
 }
 
 bool can_inline_unary_op(CoreIR::Module *module, bool _inline) {
@@ -121,6 +137,14 @@ bool can_inline_unary_op(CoreIR::Module *module, bool _inline) {
              verilog_json["primitive_type"] == "unaryReduce")
             && _inline;
     }
+    if (module->getMetaData().count("verilog") > 0) {
+        json verilog_json =
+            module->getMetaData()["verilog"];
+        return module->hasPrimitiveExpressionLambda() &&
+            (verilog_json["primitive_type"] == "unary" ||
+             verilog_json["primitive_type"] == "unaryReduce")
+            && _inline;
+    }
     return false;
 }
 
@@ -131,7 +155,7 @@ std::unique_ptr<vAST::StructuralStatement> inline_unary_op(
     UnaryOpReplacer transformer(std::move(verilog_connections["in"]));
     return std::make_unique<vAST::ContinuousAssign>(
         std::make_unique<vAST::Identifier>(instance.first + "_out"),
-        transformer.visit(instance.second->getModuleRef()->getGenerator()->getPrimitiveExpressionLambda()()));
+        transformer.visit(get_primitive_expr(instance.second)));
 }
 
 bool can_inline_const_op(CoreIR::Module *module, bool _inline) {
@@ -161,6 +185,13 @@ bool can_inline_mux_op(CoreIR::Module *module, bool _inline) {
             verilog_json["primitive_type"] == "other" &&
             module->getName() == "mux" && _inline;
     }
+    if (module->getMetaData().count("verilog") > 0) {
+        json verilog_json =
+            module->getMetaData()["verilog"];
+        return module->hasPrimitiveExpressionLambda() &&
+            verilog_json["primitive_type"] == "other" &&
+            module->getName() == "mux" && _inline;
+    }
     return false;
 }
 
@@ -173,7 +204,7 @@ std::unique_ptr<vAST::StructuralStatement> inline_mux_op(
                             std::move(verilog_connections["sel"]));
     return std::make_unique<vAST::ContinuousAssign>(
         std::make_unique<vAST::Identifier>(instance.first + "_out"),
-        transformer.visit(instance.second->getModuleRef()->getGenerator()->getPrimitiveExpressionLambda()()));
+        transformer.visit(get_primitive_expr(instance.second)));
 }
 
 bool can_inline_slice_op(CoreIR::Module *module, bool _inline) {

diff --git a/tests/gtest/test_verilog.cpp b/tests/gtest/test_verilog.cpp
@@ -118,6 +118,28 @@ TEST(VerilogTests, TestTwoInline) {
   deleteContext(c);
 }
 
+TEST(VerilogTests, TestTwoBitInline) {
+  Context* c = newContext();
+  CoreIRLoadVerilog_corebit(c);
+  Module* top;
+
+  if (!loadFromFile(c, "two_ops_bit.json", &top)) {
+    c->die();
+  }
+  assert(top != nullptr);
+  c->setTop(top->getRefName());
+
+  const std::vector<std::string> passes = {
+    "rungenerators",
+    "removebulkconnections",
+    "flattentypes",
+    "verilog --inline"
+  };
+  c->runPasses(passes, {});
+  assertPassEq<Passes::Verilog>(c, "two_ops_bit_golden.v");
+  deleteContext(c);
+}
+
 TEST(VerilogTests, TestMuxInline) {
   Context* c = newContext();
   CoreIRLoadVerilog_coreir(c);

diff --git a/tests/gtest/two_ops_bit.json b/tests/gtest/two_ops_bit.json
@@ -0,0 +1,53 @@
+{"top":"global.Top",
+"namespaces":{
+  "global":{
+    "modules":{
+      "Top":{
+        "type":["Record",[
+          ["I","BitIn"],
+          ["I1","BitIn"],
+          ["I2","BitIn"],
+          ["I3","BitIn"],
+          ["O","Bit"],
+          ["O1","Bit"]
+        ]],
+        "instances":{
+          "bit_const_1_None":{
+            "modref":"corebit.const",
+            "modargs":{"value":["Bool",true]}
+          },
+          "magma_Bit_and_inst0":{
+            "modref":"corebit.and"
+          },
+          "magma_Bit_not_inst0":{
+            "modref":"corebit.not"
+          },
+          "magma_Bit_or_inst0":{
+            "modref":"corebit.or"
+          },
+          "magma_Bit_xor_inst0":{
+            "modref":"corebit.xor"
+          },
+          "test_mux":{
+            "modref":"corebit.mux"
+          }
+        },
+        "connections":[
+          ["magma_Bit_and_inst0.in1","bit_const_1_None.out"],
+          ["magma_Bit_not_inst0.out","magma_Bit_and_inst0.in0"],
+          ["magma_Bit_or_inst0.in1","magma_Bit_and_inst0.out"],
+          ["self.I","magma_Bit_not_inst0.in"],
+          ["magma_Bit_xor_inst0.out","magma_Bit_or_inst0.in0"],
+          ["self.O","magma_Bit_or_inst0.out"],
+          ["self.I","magma_Bit_xor_inst0.in0"],
+          ["self.I","magma_Bit_xor_inst0.in1"],
+          ["self.I1","test_mux.in0"],
+          ["self.I2","test_mux.in1"],
+          ["self.I3","test_mux.sel"],
+          ["self.O1","test_mux.out"]
+        ]
+      }
+    }
+  }
+}
+}
diff --git a/tests/gtest/two_ops_bit_golden.v b/tests/gtest/two_ops_bit_golden.v
@@ -0,0 +1,5 @@
+module Top (input I, input I1, input I2, input I3, output O, output O1);
+assign O = (I ^ I) | ((~ I) & 1'b1);
+assign O1 = I3 ? I2 : I1;
+endmodule
+