Merge pull request #8 from duncangraham-Imperas/v20200619.0

vector v0.9 sstatus.VS field update : v20200619.0

ChangeLog.md

@@ -11,6 +11,14 @@ NOTE: X-commit messages below refer to git commits in the following
   I-commit: https://github.com/riscv/riscv-isa-manual
   V-commit: https://github.com/riscv/riscv-v-spec
 
+- Vector Extension
+  - sstatus.VS field alias has been implemented in its new position (from
+    specification version 0.9).
+
+Date 2020-June-17
+Release 20200616.0
+===
+
 - Core-Local Interrupt Controller (CLIC)
   - address for xintthresh CSRs have been changed to 0xm47 (previously 0xm4A)
 - Vector Extension

README.md

@@ -4,8 +4,8 @@ A Complete, Fully Functional, Configurable RISC-V Simulator
 ===
 
 Author: Imperas Software, Ltd., using OVP Open Standard APIs  
-Date   : 16 Jun 2020 
-Version: 20200616.0  
+Date   : 19 Jun 2020 
+Version: 20200619.0  
 License: Model source included under Apache 2.0 open source license  
 License: Simulator riscvOVPsim licensed under Open Virtual Platforms (OVP) Fixed Platform Kits license  
 RISC-V Specifications currently supported:

source/riscvCSR.c

@@ -2966,7 +2966,7 @@ inline static riscvCSRAttrsCP getEntryCSRAttrs(vmiRangeEntryP entry) {
 //
 // Register new CSR
 //
-void riscvNewCSR(riscvCSRAttrsCP attrs, riscvP riscv) {
+static void newCSR(riscvCSRAttrsCP attrs, riscvP riscv) {
 
     Uns32           csrNum = attrs->csrNum;
     vmiRangeTablePP tableP = &riscv->csrTable;
@@ -2981,6 +2981,43 @@ void riscvNewCSR(riscvCSRAttrsCP attrs, riscvP riscv) {
     vmirtSetRangeEntryUserData(entry, (UnsPS)attrs);
 }
 
+//
+// Adjust the given vmiReg for a register in the extension object so that it
+// can be accessed from the processor
+//
+static vmiReg getObjectReg(riscvP riscv, vmiosObjectP object, vmiReg reg) {
+
+    UnsPS delta = (UnsPS)object - (UnsPS)riscv;
+
+    return VMI_REG_DELTA(reg, delta);
+}
+
+//
+// Register new externally-implemented CSR
+//
+void riscvNewCSR(
+    riscvCSRAttrsP  attrs,
+    riscvCSRAttrsCP src,
+    riscvP          riscv,
+    vmiosObjectP    object
+) {
+    // fill attributes from template
+    if(src) {
+        *attrs = *src;
+    }
+
+    // save client object
+    attrs->object = object;
+
+    // adjust any vmiReg offsets to include object offset
+    attrs->reg32        = getObjectReg(riscv, object, attrs->reg32);
+    attrs->reg64        = getObjectReg(riscv, object, attrs->reg64);
+    attrs->writeMaskV32 = getObjectReg(riscv, object, attrs->writeMaskV32);
+    attrs->writeMaskV64 = getObjectReg(riscv, object, attrs->writeMaskV64);
+
+    newCSR(attrs, riscv);
+}
+
 //
 // Return CSR attributes for the given CSR index
 //
@@ -3411,7 +3448,7 @@ void riscvCSRInit(riscvP riscv, Uns32 index) {
     // insert all standard CSRs into CSR lookup table
     for(id=0; id<CSR_ID(LAST); id++) {
         if(RISCV_PRIV_VERSION(riscv) >= csrs[id].version) {
-            riscvNewCSR(&csrs[id], riscv);
+            newCSR(&csrs[id], riscv);
         }
     }
 

source/riscvCSR.h

@@ -328,9 +328,14 @@ typedef struct riscvCSRDetailsS {
 Bool riscvGetCSRDetails(riscvP riscv, riscvCSRDetailsP details, Bool normal);
 
 //
-// Register new CSR
+// Register new externally-implemented CSR
 //
-void riscvNewCSR(riscvCSRAttrsCP attrs, riscvP riscv);
+void riscvNewCSR(
+    riscvCSRAttrsP  attrs,
+    riscvCSRAttrsCP src,
+    riscvP          riscv,
+    vmiosObjectP    object
+);
 
 
 ////////////////////////////////////////////////////////////////////////////////
@@ -584,8 +589,8 @@ typedef CSR_REG_TYPE(status) CSR_REG_TYPE(ustatus);
 typedef CSR_REG_TYPE(status) CSR_REG_TYPE(sstatus);
 typedef CSR_REG_TYPE(status) CSR_REG_TYPE(mstatus);
 
-// define alias masks
-#define sstatus_AMASK 0x80000003818de133ULL
+// define alias masks (include sstatus.VS field in both 0.8 and 0.9 positions)
+#define sstatus_AMASK 0x80000003818de733ULL
 #define ustatus_AMASK 0x0000000000000011ULL
 
 // define bit masks