Merge pull request #52 from duncangraham-Imperas/v20200330.0

Interrupt handling for simulataneous interrupts at same priority level and vector extension update to generate exception when rounding mode invalid : v20200330.0

ChangeLog.md

@@ -11,6 +11,18 @@ NOTE: X-commit messages below refer to git commits in the following
   I-commit: https://github.com/riscv/riscv-isa-manual
   V-commit: https://github.com/riscv/riscv-v-spec
 
+- The priority order for handling simultaneous interrupts destined for the
+  same privilege level has been corrected (previously, these were handled so
+  that higher interrupt numbers were higher priority).
+- Some Vector Extension issues have been corrected:
+  - All vector floating point instructions now generate Illegal Instruction
+    exceptions if the current rounding mode is invalid, even if those
+    instructions do not use the rounding mode.
+
+Date 2020-March-13
+Release 20200312.0
+===
+
 - Support for Debug mode has been added; see RISCV processor documentation for
   more details.
 - The priv_version parameter now includes a choice of 'master', which specifies

README.md

@@ -4,8 +4,8 @@ A Complete, Fully Functional, Configurable RISC-V Simulator
 ===
 
 Author: Imperas Software, Ltd., using OVP Open Standard APIs  
-Date   : 12 Mar 2020 
-Version: 20200312.0  
+Date   : 30 Mar 2020 
+Version: 20200330.0  
 License: Model source included under Apache 2.0 open source license  
 License: Simulator riscvOVPsim licensed under Open Virtual Platforms (OVP) Fixed Platform Kits license  
 RISC-V Specifications currently supported:

examples/CoreMark/RUN_RV32_CoreMark.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

examples/bitmanip/RUN_RV64GC_BITMANIP_EXAMPLE.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

examples/dhrystone/DEBUG_GDB_RV32_dhrystone.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 

examples/dhrystone/RUN_RV32_dhrystone.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

examples/dhrystone/RUN_RV64_dhrystone.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

examples/fibonacci/RUN_RV32_fibonacci.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

examples/fibonacci/RUN_RV64_fibonacci.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

examples/fibonacci/RUN_RV64_fibonacci_signature_dump.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

examples/linpack/RUN_RV32_linpack.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

examples/vector/RUN_RV64GC_VECTOR_EXAMPLE.sh

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 cd $(dirname $0)
 bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

source/riscvAttrs.c

@@ -101,7 +101,6 @@ const vmiIASAttr modelAttrs = {
     .wrAbortExceptCB    = riscvWrAbortExcept,
     .ifetchExceptCB     = riscvIFetchExcept,
     .arithResultCB      = riscvArithResult,
-    .icountExceptCB     = riscvStepExcept,
 
     ////////////////////////////////////////////////////////////////////////
     // PARAMETER SUPPORT ROUTINES

source/riscvBus.c

@@ -84,8 +84,8 @@ void riscvNewRootBusPorts(riscvP riscv) {
     riscvBusPortPP tail  = &riscv->busPorts;
     Uns32          xlen  = riscvGetXlenArch(riscv);
     Uns32          min   = 32;
-    Uns32          max   = (xlen==32) ? RISCV_PMP_BITS_32 : RISCV_PMP_BITS_64;
-    Uns32          unset = max;
+    Uns32          unset = (xlen==32) ? RISCV_PMP_BITS_32 : RISCV_PMP_BITS_64;
+    Uns32          max   = (xlen==32) ? RISCV_PMP_BITS_32 : 64;
 
     // instruction port
     newBusPort(