Merge pull request #4 from jstraus59/v20200526.0

Fix errors in v20200521.0 release : v20200526.0

ChangeLog.md

@@ -11,6 +11,13 @@ NOTE: X-commit messages below refer to git commits in the following
   I-commit: https://github.com/riscv/riscv-isa-manual
   V-commit: https://github.com/riscv/riscv-v-spec
 
+- Memory accesses that straddle PMP region boundaries are now disallowed for
+  M-mode, even if those regions imply full M-mode access.
+
+Date 2020-May-22
+Release 20200521.0
+===
+
 - Memory accesses that straddle PMP region boundaries are now disallowed.
 - EBREAK now sets tval to 0 if priv_version is set to master.
 - Some Vector Extension issues have been corrected:

README.md

@@ -4,8 +4,8 @@ A Complete, Fully Functional, Configurable RISC-V Simulator
 ===
 
 Author: Imperas Software, Ltd., using OVP Open Standard APIs  
-Date   : 21 May 2020 
-Version: 20200521.0  
+Date   : 26 May 2020 
+Version: 20200526.0  
 License: Model source included under Apache 2.0 open source license  
 License: Simulator riscvOVPsim licensed under Open Virtual Platforms (OVP) Fixed Platform Kits license  
 RISC-V Specifications currently supported:

source/riscvCSR.c

@@ -2584,7 +2584,7 @@ static RISCV_CSR_WRITEFN(dcsrW) {
 static const riscvCSRAttrs csrs[CSR_ID(LAST)] = {
 
     //                name          num    arch         access      version   attrs    description                                      present wState       rCB           rwCB      wCB
-    CSR_ATTR_P__     (ustatus,      0x000, ISA_N,       0,          1_10,   0,0,0,0,0, "User Status",                                   0,      0,           ustatusR,     0,        ustatusW      ),
+    CSR_ATTR_P__     (ustatus,      0x000, ISA_N,       0,          1_10,   0,0,0,0,1, "User Status",                                   0,      0,           ustatusR,     0,        ustatusW      ),
     CSR_ATTR_P__     (fflags,       0x001, ISA_DF,      0,          1_10,   0,0,0,0,0, "Floating-Point Flags",                          0,      riscvWFS,    fflagsR,      0,        fflagsW       ),
     CSR_ATTR_P__     (frm,          0x002, ISA_DF,      0,          1_10,   1,0,0,0,0, "Floating-Point Rounding Mode",                  0,      riscvWFS,    frmR,         0,        frmW          ),
     CSR_ATTR_P__     (fcsr,         0x003, ISA_DFV,     ISA_FS,     1_10,   1,0,0,0,0, "Floating-Point Control and Status",             0,      riscvWFS,    fcsrR,        0,        fcsrW         ),
@@ -2617,7 +2617,7 @@ static const riscvCSRAttrs csrs[CSR_ID(LAST)] = {
     CSR_ATTR_P__3_31 (hpmcounterh,  0xC80, ISA_XLEN_32, 0,          1_10,   0,0,0,0,0, "Performance Monitor High ",                     0,      0,           mhpmR,        0,        0             ),
 
     //                name          num    arch         access      version   attrs    description                                      present wState       rCB           rwCB      wCB
-    CSR_ATTR_P__     (sstatus,      0x100, ISA_S,       0,          1_10,   0,0,0,0,0, "Supervisor Status",                             0,      riscvRstFS,  sstatusR,     0,        sstatusW      ),
+    CSR_ATTR_P__     (sstatus,      0x100, ISA_S,       0,          1_10,   0,0,0,0,1, "Supervisor Status",                             0,      riscvRstFS,  sstatusR,     0,        sstatusW      ),
     CSR_ATTR_TV_     (sedeleg,      0x102, ISA_SandN,   0,          1_10,   0,0,0,0,0, "Supervisor Exception Delegation",               0,      0,           0,            0,        0             ),
     CSR_ATTR_T__     (sideleg,      0x103, ISA_SandN,   0,          1_10,   1,0,0,0,0, "Supervisor Interrupt Delegation",               0,      0,           0,            0,        sidelegW      ),
     CSR_ATTR_P__     (sie,          0x104, ISA_S,       0,          1_10,   1,0,0,0,0, "Supervisor Interrupt Enable",                   0,      0,           sieR,         0,        sieW          ),

source/riscvExceptions.c

@@ -2212,10 +2212,73 @@ static void updateCLICInterruptField(
 }
 
 //
-// Return rending for the indexed interrupt
+// Return clicintattr for the indexed interrupt
+//
+inline static CLIC_REG_TYPE(clicintattr) getCLICInterruptAttr(
+    riscvP hart,
+    Uns32  intIndex
+) {
+    CLIC_REG_DECL(clicintattr) = {
+        bits:getCLICInterruptField(hart, intIndex, CIT_clicintattr)
+    };
+
+    return clicintattr;
+}
+
+//
+// Is the indexed interrupt edge triggered?
+//
+inline static Bool isCLICInterruptEdge(riscvP hart, Uns32 intIndex) {
+
+    CLIC_REG_DECL(clicintattr) = getCLICInterruptAttr(hart, intIndex);
+
+    return clicintattr.fields.trig&1;
+}
+
+//
+// Is the indexed interrupt active low?
+//
+inline static Bool isCLICInterruptActiveLow(riscvP hart, Uns32 intIndex) {
+
+    CLIC_REG_DECL(clicintattr) = getCLICInterruptAttr(hart, intIndex);
+
+    return clicintattr.fields.trig&2;
+}
+
 //
-inline static Bool getCLICInterruptPending(riscvP hart, Uns32 intIndex) {
-    return getCLICInterruptField(hart, intIndex, CIT_clicintip);
+// Return pending for the indexed interrupt
+//
+static Bool getCLICInterruptPending(riscvP hart, Uns32 intIndex) {
+
+    // get latched pending bit
+    Bool IP = getCLICInterruptField(hart, intIndex, CIT_clicintip);
+
+    // for level-triggered interrupts, include the unlatched external source
+    if(!isCLICInterruptEdge(hart, intIndex)) {
+
+        Uns32 wordIndex  = intIndex/64;
+        Uns64 mask       = (1ULL<<(intIndex%64));
+        Bool  externalIP = hart->ip[wordIndex] & mask;
+
+        IP |= externalIP;
+    }
+
+    return IP;
+}
+
+//
+// Set pending for the indexed interrupt
+//
+inline static void setCLICInterruptPending(
+    riscvP hart,
+    Uns32  intIndex,
+    Bool   newValue,
+    Bool   isStore
+) {
+    // level-triggered pending values are not latched
+    if(isStore || isCLICInterruptEdge(hart, intIndex)) {
+        setCLICInterruptField(hart, intIndex, CIT_clicintip, newValue);
+    }
 }
 
 //
@@ -2226,17 +2289,25 @@ inline static Bool getCLICInterruptEnable(riscvP hart, Uns32 intIndex) {
 }
 
 //
-// Return clicintattr for the indexed interrupt
+// Set enable for the indexed interrupt
 //
-inline static CLIC_REG_TYPE(clicintattr) getCLICInterruptAttr(
+inline static void setCLICInterruptEnable(
     riscvP hart,
-    Uns32  intIndex
+    Uns32  intIndex,
+    Bool   newValue
 ) {
-    CLIC_REG_DECL(clicintattr) = {
-        bits:getCLICInterruptField(hart, intIndex, CIT_clicintattr)
-    };
+    setCLICInterruptField(hart, intIndex, CIT_clicintie, newValue);
+}
 
-    return clicintattr;
+//
+// Return CLIC pending+enabled state for the given interrupt
+//
+static Bool getCLICPendingEnable(riscvP hart, Uns32 intIndex) {
+
+    Uns32 wordIndex = intIndex/64;
+    Uns64 mask      = (1ULL<<(intIndex%64));
+
+    return hart->clic.ipe[wordIndex] & mask;
 }
 
 //
@@ -2245,8 +2316,7 @@ inline static CLIC_REG_TYPE(clicintattr) getCLICInterruptAttr(
 static void updateCLICPendingEnable(riscvP hart, Uns32 intIndex, Bool newIPE) {
 
     Uns32 wordIndex = intIndex/64;
-    Uns32 bitIndex  = intIndex%64;
-    Uns64 mask      = (1ULL<<bitIndex);
+    Uns64 mask      = (1ULL<<(intIndex%64));
 
     if(newIPE) {
         hart->clic.ipe[wordIndex] |= mask;
@@ -2263,15 +2333,15 @@ static void updateCLICPendingEnable(riscvP hart, Uns32 intIndex, Bool newIPE) {
 static void writeCLICInterruptPending(
     riscvP hart,
     Uns32  intIndex,
-    Uns8   newValue
+    Uns8   newValue,
+    Bool   isStore
 ) {
-    riscvCLICIntStateP intState = &hart->clic.intState[intIndex];
-    Bool               oldIE    = intState->fields[CIT_clicintie];
-    Bool               newIP    = newValue&1;
+    Bool oldIE = getCLICInterruptEnable(hart, intIndex);
+    Bool newIP = newValue&1;
 
     // update field, detecting change in pending+enabled
-    Bool oldIPE = oldIE && intState->fields[CIT_clicintip];
-    intState->fields[CIT_clicintip] = newIP;
+    Bool oldIPE = getCLICPendingEnable(hart, intIndex);
+    setCLICInterruptPending(hart, intIndex, newIP, isStore);
     Bool newIPE = oldIE && newIP;
 
     // update state if pending+enabled has changed
@@ -2288,13 +2358,12 @@ static void writeCLICInterruptEnable(
     Uns32  intIndex,
     Uns8   newValue
 ) {
-    riscvCLICIntStateP intState = &hart->clic.intState[intIndex];
-    Bool               oldIP    = intState->fields[CIT_clicintip];
-    Bool               newIE    = newValue&1;
+    Bool oldIP = getCLICInterruptPending(hart, intIndex);
+    Bool newIE = newValue&1;
 
     // update field, detecting change in pending+enabled
-    Bool oldIPE = oldIP && intState->fields[CIT_clicintie];
-    intState->fields[CIT_clicintie] = newIE;
+    Bool oldIPE = getCLICPendingEnable(hart, intIndex);
+    setCLICInterruptEnable(hart, intIndex, newIE);
     Bool newIPE = oldIP && newIE;
 
     // update state if pending+enabled has changed
@@ -2438,7 +2507,16 @@ static Uns32 readCLICInterrupt(riscvP root, Uns32 offset) {
         riscvP hart     = getCLICHart(root, offset);
         Uns32  intIndex = getCLICIntIndex(offset);
 
-        result = getCLICInterruptValue(hart, intIndex);
+        switch(getCLICIntFieldType(offset)) {
+
+            case CIT_clicintip:
+                result = getCLICInterruptPending(hart, intIndex);
+                break;
+
+            default:
+                result = getCLICInterruptValue(hart, intIndex);
+                break;
+        }
     }
 
     return result;
@@ -2458,7 +2536,7 @@ static void writeCLICInterrupt(riscvP root, Uns32 offset, Uns8 newValue) {
         switch(getCLICIntFieldType(offset)) {
 
             case CIT_clicintip:
-                writeCLICInterruptPending(hart, intIndex, newValue);
+                writeCLICInterruptPending(hart, intIndex, newValue, True);
                 break;
 
             case CIT_clicintie:
@@ -2630,7 +2708,7 @@ static void refreshPendingAndEnabledCLIC(riscvP hart) {
 }
 
 //
-// Refresh CliC pending+enable mask (after restore)
+// Refresh CLIC pending+enable mask (after restore)
 //
 static void refreshCLICIPE(riscvP hart) {
 
@@ -2663,14 +2741,9 @@ static void refreshCLICIPE(riscvP hart) {
 //
 void riscvAcknowledgeCLICInt(riscvP hart, Uns32 intIndex) {
 
-    CLIC_REG_DECL(clicintattr) = getCLICInterruptAttr(hart, intIndex);
-
-    // determine interrupt configuration
-    Bool isEdge = clicintattr.fields.trig&1;
-
     // deassert interrupt if edge triggered, or refresh pending state if not
-    if(isEdge) {
-        writeCLICInterruptPending(hart, intIndex, 0);
+    if(isCLICInterruptEdge(hart, intIndex)) {
+        writeCLICInterruptPending(hart, intIndex, 0, False);
     } else {
         refreshPendingAndEnabled(hart);
     }
@@ -2681,18 +2754,16 @@ void riscvAcknowledgeCLICInt(riscvP hart, Uns32 intIndex) {
 //
 static void updateCLICInput(riscvP hart, Uns32 intIndex, Bool newValue) {
 
-    CLIC_REG_DECL(clicintattr) = getCLICInterruptAttr(hart, intIndex);
-
     // determine interrupt configuration
-    Bool isEdge    = clicintattr.fields.trig&1;
-    Bool activeLow = clicintattr.fields.trig&2;
+    Bool isEdge    = isCLICInterruptEdge(hart, intIndex);
+    Bool activeLow = isCLICInterruptActiveLow(hart, intIndex);
 
     // handle active low inputs
     newValue ^= activeLow;
 
     // apply new value if either level triggered or edge triggered and asserted
     if(!isEdge || newValue) {
-        writeCLICInterruptPending(hart, intIndex, newValue);
+        writeCLICInterruptPending(hart, intIndex, newValue, False);
     }
 }
 
@@ -3533,7 +3604,7 @@ void riscvNetRestore(
                 sizeof(*riscv->clic.intState)*getIntNum(riscv)
             );
 
-            // refresh CliC pending+enable mask
+            // refresh CLIC pending+enable mask
             refreshCLICIPE(riscv);
         }
 

source/riscvMorph.c

@@ -5969,7 +5969,7 @@ static riscvVLClassMt fillVectorOperationData(
     if(state->info.isWhole) {
         id->VLMULx8 = VLMULx8MT_1;
         id->VLEN    = riscv->configInfo.VLEN * (state->info.nf+1);
-        id->SEW     = SEWMT_8;
+        id->SEW     = riscv->configInfo.SEW_min;
         id->SLEN    = vectorFractLMUL(riscv) ? riscv->configInfo.SLEN : id->VLEN;
         id->nf      = 0;
         vlClass     = VLCLASSMT_MAX;