Imperas Risc-V OVPsim Release v20200518.0

riscvOVPsim Change Log

Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com

This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model

---

NOTE: X-commit messages below refer to git commits in the following
Risc-V specification document repositories:
I-commit: https://github.com/riscv/riscv-isa-manual
V-commit: https://github.com/riscv/riscv-v-spec

Date 2020-May-18
Release 20200518.0

• EBREAK and ECALL no longer count as retired instructions if priv_version
  is set to master.
• SC instruction behavior has been changed so that store address alignment is
  validated even if the reservation check fails (previously, alignment was
  validated only if the reservation check succeeded).
• Masking of the mcountinhibit CSR has been corrected - previously, bit 1 and
  bits 63...32 were writeable when they should have been 0.
• The nmi signal has been corrected to match the documented behavior, execution
  resumes at the nmi_address parameter value when the nmi signal goes high
• The optional Core-Local Interrupt Controller (CLIC) has been implemented
  (version 0.9-draft-20191208).
• Vector version 0.9 has been added, and is now used by default. Differences
  compared to the previous 0.8 version are as follows (with the associated
  specification V-commit identifiers):
  • V-commit bdb8b55: mstatus.VS and sstatus.VS fields have moved to bits 10:9;
  • V-commit b25b643: new CSR vcsr has been added and fields VXSAT and VXRM
    fields relocated there from CSR fcsr;
  • V-commit 951b64f: mirrors of fcsr fields have been removed from vcsr.
  • V-commit 1aceea2: vfslide1up.vf and vfslide1down.vf instructions added.
  • V-commit e256d65: vfcvt.rtz.xu.f.v, vfcvt.rtz.x.f.v, vfwcvt.rtz.xu.f.v,
    vfwcvt.rtz.x.f.v, vfncvt.rtz.xu.f.v and vfncvt.rtz.x.f.v instructions added;
  • V-commit 8a9fbce (and others): fractional LMUL support added, controlled by
    an extended vtype.vlmul CSR field;
  • V-commit f414f4d (and others): vector tail agnostic and vector mask agnostic
    fields added to the vtype CSR;
  • V-commit a526fb9 (and others): all vector load/store instructions replaced
    with new instructions that explicitly encode EEW of data or index;
  • V-commit ef531ea: whole register load and store operation encodings changed;
  • V-commit bdc85cd: vzext.vf2, vsext.vf2, vzext.vf4, vsext.vf4, vzext.vf8 and
    vsext.vf8 instructions added;
  • V-commit 9a77e12: MLEN is always 1.
• Some Vector Extension issues have been corrected:
  • Instructions vfmv.s.f and vfmv.f.s now require that SEW is a supported
    floating point size (pending vector specification clarification).