Imperas Risc-V OVPsim Release v20200608.0

riscvOVPsim Change Log

Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com

This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model

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Date 2020-Jun-08
Release 20200608.0

NOTE: X-commit messages below refer to git commits in the following
Risc-V specification document repositories:
I-commit: https://github.com/riscv/riscv-isa-manual
V-commit: https://github.com/riscv/riscv-v-spec

• The Bit-Manipulation Extension is now implemented in the model, with version
  defined by parameter bitmanip_version.
• Some Vector Extension issues have been corrected:
  • Parameter order shown by disassembly of vector AMO instructions has been
    corrected. Model behavior is not affected by this change.
  • Encodings of integer extension instructions have been corrected for Vector
    Extension version 0.9.
• The vector version master branch currently has these differences compared to
  the previous 0.9 version:
  • V-commit 443ce5b: overlap constraints for different source/destination EEW
    changed.