Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Baremetal patch #6

Open
wants to merge 2 commits into
base: master
Choose a base branch
from
Open

Baremetal patch #6

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
28daaf6
Fixed Baremetal built for spike and FPGAs
May 20, 2020
3413d1f
Documented changes in readme
Matthias-Raudonis May 20, 2020
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 3 additions & 1 deletion README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,9 @@ This repository provides the utility files to port [CoreMark EEMBC](https://www.
- Builds a version of Coremark for Linux or pk (coremark.riscv)
- Builds a version of Coremark for bare-metal (coremark.bare.riscv)
- Copies the output binaries into this directory

### Bare-metal core frequency
- To define the bare-metal core frequency, edit `BAREMETAL_CORE_FREQ` in `./riscv64-baremetal/core_portme.h`
- The default value has been set to 1Mhz to reduce execution time on spike and FPGAs.
### Default Files

The default files target **RV64GC** and use minimal amount of compilation flags. Additionally, the `*.mak` file in the `riscv64`
Expand Down
2 changes: 1 addition & 1 deletion riscv64-baremetal/core_portme.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -108,7 +108,7 @@ void portable_free(void *p) {
#define SAMPLE_TIME_IMPLEMENTATION 1
#else
// Defined for RISCV
#define NSECS_PER_SEC 1000000000 // TODO: What freq are we assuming?
#define NSECS_PER_SEC BAREMETAL_CORE_FREQ // Frequency defined in core_portme.h
#define EE_TIMER_TICKER_RATE 1000 // TODO: What is this?
#define CORETIMETYPE clock_t
#define read_csr(reg) ({ unsigned long __tmp; \
Expand Down
9 changes: 8 additions & 1 deletion riscv64-baremetal/core_portme.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,11 +24,18 @@ Original Author: Shay Gal-on
/************************/
/* Data types and settings */
/************************/
/* Configuration: Used or assumed core frequency in MHz
Must be low enough to run on spike or FPGAs.
*/
#ifndef BAREMETAL_CORE_FREQ
#define BAREMETAL_CORE_FREQ 1000000 // 1 MHz
#endif

/* Configuration: HAS_FLOAT
Define to 1 if the platform supports floating point.
*/
#ifndef HAS_FLOAT
#define HAS_FLOAT 1
#define HAS_FLOAT 0 // The used syscalls.c doesn't have float implemented. Coremark does not test float.
#endif
/* Configuration: HAS_TIME_H
Define to 1 if platform has the time.h header file,
Expand Down