Fixed the overlapping operands to resolve the illegal instruction exc…

…eption issue (#501) Co-authored-by: Umer Shahid <[email protected]>
riscv-non-isa · Nov 7, 2024 · 13fb359 · 13fb359
1 parent c6b1faa
commit 13fb359
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vsha2ms-e32.vv-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vsha2ms-e32.vv-01.S
@@ -70,7 +70,7 @@ TEST_CASE_WVV(4, 32, VINST, v15, 2*4, v14, 3*4, v18, 8*4)
 //sig[116*4]
 
 inst_8:
-TEST_CASE_WVV(4, 32, VINST, v16, 0*4, v17, 4*4, v16, 0*4)
+TEST_CASE_WVV(4, 32, VINST, v18, 0*4, v17, 4*4, v16, 0*4)
 //sig[120*4]
 
 inst_9: