Updated changes => adjusted #endif at one place

riscv-test-suite/env/arch_test.h

@@ -849,7 +849,7 @@ RVMODEL_DATA_END        /* model specific stuff */
         /**** set MEPC to mret+4; requires relocating the pc   ****/
 .if     (\LMODE\() == Vmode)     // get trapsig_ptr & init val up 2 save areas (M<-S<-V)
         LREG    T1, code_bgn_off + 2*sv_area_sz(sp)
-.elseif (\LMODE\() == Smode)     // get trapsig_ptr & init val up 1 save areas (M<-S)
+.elseif (\LMODE\() == Smode || \LMODE\() == Umode)     // get trapsig_ptr & init val up 1 save areas (M<-S)
         LREG    T1, code_bgn_off + 1*sv_area_sz(sp)
 .else                            // get trapsig ptr & init val for this Mmode, (M)
         LREG    T1, code_bgn_off + 0*sv_area_sz(sp)
@@ -1305,9 +1305,9 @@ common_\__MODE__\()excpt_handler:
         srli    T3, T3, GVA_LSB-1       /* reposition RV32 mstatush into bit1   */
       #else
         srli    T3, T6, GVA_LSB-1+32    /* reposition RV32 mstatus  into bit1   */
+      #endif
         andi    T3, T3, 1<<1
         or      T4, T4, T3              /* extract GVA in bit1, insert into msk */
-    #endif
 // put H-extension implemented into bit 0       
         ori     T4, T4, 1               /* set LSB if H-ext present             */
         //****FIXME: this doesn't work if misa.H is RW but set to zero ****/