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add support for cbo.zero in cmo extension
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Weiwei Li committed Feb 23, 2023
1 parent a3b7f0c commit 4de22d2
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14 changes: 14 additions & 0 deletions coverage/rvi_cmo.cgf
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# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore

cbozero:
config:
- check ISA:=regex(.*I.*Zicboz.*Zicsr.*)
opcode:
cbo.zero: 0
rs1:
<<: *all_regs_mx0
val_comb:
abstract_comb:
'walking_ones("rs1_val", 12, False)': 0
'walking_zeros("rs1_val", 12, False)': 0
'uniform_random(10, 100, ["rs1_val"], [12])': 0
13 changes: 13 additions & 0 deletions riscv-test-suite/env/test_macros.h
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Expand Up @@ -391,6 +391,19 @@ nop ;\
csrr flagreg, fcsr ;\
RVTEST_SIGUPD_F(swreg,destreg,flagreg)

#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val) ;\
LI(rs1,imm_val&(BLOCKSZ-1)) ;\
add rs1,rs1,swreg ;\
inst (rs1) ;\
nop ;\
nop ;\
#if (BLOCKSZ<4096) \
addi swreg, swreg, BLOCKSZ ;\
#else ;\
LI(rs1, BLOCKSZ) \
add swreg,swreg,rs1 ;\
#endif

#define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) ;\
LI(TEMP_REG,VAL) ;\
and TEMP_REG,TEMP_REG,MASK_REG ;\
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312 changes: 312 additions & 0 deletions riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S
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// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.10.4
// timestamp : Wed Feb 22 09:04:22 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /workspace/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /workspace/riscv-ctg/sample_cgfs/rv32i_cbo.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the cbo.zero instruction of the RISC-V RV32ZicbozZicsr extension for the cbozero covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IZicbozZicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero)

RVTEST_SIGBASE(x2,signature_x2_1)

inst_0:
// rs1==x30, rs1_val == 0x4a9
// opcode: cbo.zero ; op1:x30; op1val:0x4a9
TEST_CBO_ZERO(x2,x30,cbo.zero,0x4a9)

inst_1:
// rs1==x9, rs1_val == 0xeb4
// opcode: cbo.zero ; op1:x9; op1val:0xeb4
TEST_CBO_ZERO(x2,x9,cbo.zero,0xeb4)

inst_2:
// rs1==x22, rs1_val == 0xe8e
// opcode: cbo.zero ; op1:x22; op1val:0xe8e
TEST_CBO_ZERO(x2,x22,cbo.zero,0xe8e)

inst_3:
// rs1==x27, rs1_val == 0x597
// opcode: cbo.zero ; op1:x27; op1val:0x597
TEST_CBO_ZERO(x2,x27,cbo.zero,0x597)

inst_4:
// rs1==x16, rs1_val == 4094,
// opcode: cbo.zero ; op1:x16; op1val:0xffe
TEST_CBO_ZERO(x2,x16,cbo.zero,0xffe)

inst_5:
// rs1==x12, rs1_val == 4093,
// opcode: cbo.zero ; op1:x12; op1val:0xffd
TEST_CBO_ZERO(x2,x12,cbo.zero,0xffd)

inst_6:
// rs1==x21, rs1_val == 4091,
// opcode: cbo.zero ; op1:x21; op1val:0xffb
TEST_CBO_ZERO(x2,x21,cbo.zero,0xffb)

inst_7:
// rs1==x28, rs1_val == 4087,
// opcode: cbo.zero ; op1:x28; op1val:0xff7
TEST_CBO_ZERO(x2,x28,cbo.zero,0xff7)

inst_8:
// rs1==x25, rs1_val == 4079,
// opcode: cbo.zero ; op1:x25; op1val:0xfef
TEST_CBO_ZERO(x2,x25,cbo.zero,0xfef)

inst_9:
// rs1==x6, rs1_val == 4063,
// opcode: cbo.zero ; op1:x6; op1val:0xfdf
TEST_CBO_ZERO(x2,x6,cbo.zero,0xfdf)

inst_10:
// rs1==x1, rs1_val == 4031,
// opcode: cbo.zero ; op1:x1; op1val:0xfbf
TEST_CBO_ZERO(x2,x1,cbo.zero,0xfbf)

inst_11:
// rs1==x4, rs1_val == 3967,
// opcode: cbo.zero ; op1:x4; op1val:0xf7f
TEST_CBO_ZERO(x2,x4,cbo.zero,0xf7f)

inst_12:
// rs1==x7, rs1_val == 3839,
// opcode: cbo.zero ; op1:x7; op1val:0xeff
TEST_CBO_ZERO(x2,x7,cbo.zero,0xeff)

inst_13:
// rs1==x3, rs1_val == 3583,
// opcode: cbo.zero ; op1:x3; op1val:0xdff
TEST_CBO_ZERO(x2,x3,cbo.zero,0xdff)

inst_14:
// rs1==x18, rs1_val == 3071,
// opcode: cbo.zero ; op1:x18; op1val:0xbff
TEST_CBO_ZERO(x2,x18,cbo.zero,0xbff)

inst_15:
// rs1==x10, rs1_val == 2047,
// opcode: cbo.zero ; op1:x10; op1val:0x7ff
TEST_CBO_ZERO(x2,x10,cbo.zero,0x7ff)

inst_16:
// rs1==x8, rs1_val == 1,
// opcode: cbo.zero ; op1:x8; op1val:0x1
TEST_CBO_ZERO(x2,x8,cbo.zero,0x1)

inst_17:
// rs1==x23, rs1_val == 2,
// opcode: cbo.zero ; op1:x23; op1val:0x2
TEST_CBO_ZERO(x2,x23,cbo.zero,0x2)

inst_18:
// rs1==x13, rs1_val == 4,
// opcode: cbo.zero ; op1:x13; op1val:0x4
TEST_CBO_ZERO(x2,x13,cbo.zero,0x4)

inst_19:
// rs1==x17, rs1_val == 8,
// opcode: cbo.zero ; op1:x17; op1val:0x8
TEST_CBO_ZERO(x2,x17,cbo.zero,0x8)

inst_20:
// rs1==x31, rs1_val == 16,
// opcode: cbo.zero ; op1:x31; op1val:0x10
TEST_CBO_ZERO(x2,x31,cbo.zero,0x10)

inst_21:
// rs1==x29, rs1_val == 32,
// opcode: cbo.zero ; op1:x29; op1val:0x20
TEST_CBO_ZERO(x2,x29,cbo.zero,0x20)

inst_22:
// rs1==x11, rs1_val == 64,
// opcode: cbo.zero ; op1:x11; op1val:0x40
TEST_CBO_ZERO(x2,x11,cbo.zero,0x40)

inst_23:
// rs1==x5, rs1_val == 128,
// opcode: cbo.zero ; op1:x5; op1val:0x80
TEST_CBO_ZERO(x2,x5,cbo.zero,0x80)

inst_24:
// rs1==x24, rs1_val == 256,
// opcode: cbo.zero ; op1:x24; op1val:0x100
TEST_CBO_ZERO(x2,x24,cbo.zero,0x100)

inst_25:
// rs1==x15, rs1_val == 512,
// opcode: cbo.zero ; op1:x15; op1val:0x200
TEST_CBO_ZERO(x2,x15,cbo.zero,0x200)

inst_26:
// rs1==x14, rs1_val == 1024,
// opcode: cbo.zero ; op1:x14; op1val:0x400
TEST_CBO_ZERO(x2,x14,cbo.zero,0x400)

inst_27:
// rs1==x19, rs1_val == 2048,
// opcode: cbo.zero ; op1:x19; op1val:0x800
TEST_CBO_ZERO(x2,x19,cbo.zero,0x800)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_28:
// rs1==x20, rs1_val == 0xc93
// opcode: cbo.zero ; op1:x20; op1val:0xc93
TEST_CBO_ZERO(x1,x20,cbo.zero,0xc93)

inst_29:
// rs1==x26, rs1_val == 0xb31
// opcode: cbo.zero ; op1:x26; op1val:0xb31
TEST_CBO_ZERO(x1,x26,cbo.zero,0xb31)

inst_30:
// rs1==x2, rs1_val == 0xddf
// opcode: cbo.zero ; op1:x2; op1val:0xddf
TEST_CBO_ZERO(x1,x2,cbo.zero,0xddf)

inst_31:
// rs1_val == 0x384
// opcode: cbo.zero ; op1:x31; op1val:0x384
TEST_CBO_ZERO(x1,x31,cbo.zero,0x384)

inst_32:
// rs1_val == 0x3e1
// opcode: cbo.zero ; op1:x31; op1val:0x3e1
TEST_CBO_ZERO(x1,x31,cbo.zero,0x3e1)

inst_33:
// rs1_val == 0x290
// opcode: cbo.zero ; op1:x31; op1val:0x290
TEST_CBO_ZERO(x1,x31,cbo.zero,0x290)

inst_34:
// rs1_val == 0xe97
// opcode: cbo.zero ; op1:x31; op1val:0xe97
TEST_CBO_ZERO(x1,x31,cbo.zero,0xe97)

inst_35:
// rs1_val == 0x86d
// opcode: cbo.zero ; op1:x31; op1val:0x86d
TEST_CBO_ZERO(x1,x31,cbo.zero,0x86d)

inst_36:
// rs1_val == 0x188
// opcode: cbo.zero ; op1:x31; op1val:0x188
TEST_CBO_ZERO(x1,x31,cbo.zero,0x188)

inst_37:
// rs1_val == 0x68b
// opcode: cbo.zero ; op1:x31; op1val:0x68b
TEST_CBO_ZERO(x1,x31,cbo.zero,0x68b)

inst_38:
// rs1_val == 0xabb
// opcode: cbo.zero ; op1:x31; op1val:0xabb
TEST_CBO_ZERO(x1,x31,cbo.zero,0xabb)

inst_39:
// rs1_val == 0x759
// opcode: cbo.zero ; op1:x31; op1val:0x759
TEST_CBO_ZERO(x1,x31,cbo.zero,0x759)

inst_40:
// rs1_val == 0x9e6
// opcode: cbo.zero ; op1:x31; op1val:0x9e6
TEST_CBO_ZERO(x1,x31,cbo.zero,0x9e6)

inst_41:
// rs1_val == 0x686
// opcode: cbo.zero ; op1:x31; op1val:0x686
TEST_CBO_ZERO(x1,x31,cbo.zero,0x686)

inst_42:
// rs1_val == 0x5b5
// opcode: cbo.zero ; op1:x31; op1val:0x5b5
TEST_CBO_ZERO(x1,x31,cbo.zero,0x5b5)

inst_43:
// rs1_val == 0x481
// opcode: cbo.zero ; op1:x31; op1val:0x481
TEST_CBO_ZERO(x1,x31,cbo.zero,0x481)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x2_0:
.fill 0*((BLOCKSZ)/4),4,0xdeadbeef


signature_x2_1:
.fill 28*((BLOCKSZ)/4),4,0xdeadbeef


signature_x1_0:
.fill 16*((BLOCKSZ)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
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