add support for cbo.zero in cmo extension

riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include

@@ -0,0 +1,42 @@
+TARGET_SIM   ?= riscv_sim_RV32 -V
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+BLOCKSZ ?= 64
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RUN_CMD=\
+    $(TARGET_SIM) $(TARGET_FLAGS) -B $(BLOCKSZ) \
+        --test-signature=$(*).signature.output \
+        $(<)
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -DBLOCKSZ=$(BLOCKSZ) $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > [email protected]; \
+					$$(RISCV_OBJDUMP) $$@ --source > [email protected]
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_TARGET=\
+	$(RUN_CMD) 

riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include

@@ -0,0 +1,43 @@
+TARGET_SIM   ?= riscv_sim_RV64 -V
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+BLOCKSZ ?= 64
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RUN_CMD=\
+    $(TARGET_SIM) $(TARGET_FLAGS) -B $(BLOCKSZ)\
+        --test-signature=$(*).signature.output \
+        $(<)
+
+RISCV_PREFIX   ?= riscv64-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -DBLOCKSZ=$(BLOCKSZ) $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > [email protected]; \
+					$$(RISCV_OBJDUMP) $$@ --source > [email protected]
+
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_TARGET=\
+	$(RUN_CMD) 

riscv-target/sail-riscv-c/model_test.h

@@ -28,7 +28,7 @@
 
 //RV_COMPLIANCE_DATA_BEGIN
 #define RVMODEL_DATA_BEGIN                                              \
-  .align 4 ; .global begin_signature; begin_signature:
+  .align 12 ; .global begin_signature; begin_signature:
 
 //RV_COMPLIANCE_DATA_END
 #define RVMODEL_DATA_END                                                      \

riscv-test-suite/env/arch_test.h

@@ -781,6 +781,13 @@ inst rs2, imm_val(rs1)                                                      ;\
 nop                                                                         ;\
 nop                                                                         
 
+#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val)   ;\
+addi rs1,swreg,(imm_val&(BLOCKSZ-1))                                        ;\
+inst rs1                                                                    ;\
+nop                                                                         ;\
+nop                                                                         ;\
+addi swreg, swreg, BLOCKSZ
+
 #define TEST_LOAD(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj)   ;\
 LA(rs1,rvtest_data+(index*4)+adj-imm_val)                                      ;\
 inst destreg, imm_val(rs1)                                                   ;\

riscv-test-suite/rv32i_m/cmo/Makefile

@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -DXLEN=$(XLEN) -DBLOCKSZ=$(BLOCKSZ)))

riscv-test-suite/rv32i_m/cmo/Makefrag

@@ -0,0 +1,35 @@
+# RISC-V Architecture Test RV32I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32I architectural tests
+
+rv32i_sc_tests = \
+  cbo.zero-01
+
+rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
+
+target_tests += $(rv32i_tests)