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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,67 @@ | ||
| c.fld: | ||
| config: | ||
| - check ISA:=regex(.*I.*F.*D.*C.*) | ||
| mnemonics: | ||
| c.fld: 0 | ||
| rs1: | ||
| <<: *c_regs | ||
| rd: | ||
| <<: *c_fregs | ||
| op_comb: | ||
| 'rs1 != rd': 0 | ||
| val_comb: | ||
| 'imm_val > 0 and fcsr == 0': 0 | ||
| 'imm_val == 0 and fcsr == 0': 0 | ||
| abstract_comb: | ||
| 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 | ||
| 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 | ||
| 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 | ||
|
|
||
| c.fsd: | ||
| config: | ||
| - check ISA:=regex(.*I.*F.*D.*C.*) | ||
| opcode: | ||
| c.fsd: 0 | ||
| rs1: | ||
| <<: *c_regs | ||
| rs2: | ||
| <<: *c_fregs | ||
| op_comb: | ||
| 'rs1 != rs2': 0 | ||
| val_comb: | ||
| 'imm_val > 0': 0 | ||
| 'imm_val == 0': 0 | ||
| abstract_comb: | ||
| 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 | ||
| 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 | ||
| 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 | ||
|
|
||
| c.fldsp: | ||
| config: | ||
| - check ISA:=regex(.*I.*F.*D.*C.*) | ||
| opcode: | ||
| c.fldsp: 0 | ||
| rd: | ||
| <<: *all_fregs | ||
| val_comb: | ||
| 'imm_val > 0': 0 | ||
| 'imm_val == 0': 0 | ||
| abstract_comb: | ||
| 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 | ||
| 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 | ||
| 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 | ||
|
|
||
| c.fsdsp: | ||
| config: | ||
| - check ISA:=regex(.*I.*F.*D.*C.*) | ||
| opcode: | ||
| c.fsdsp: 0 | ||
| rs2: | ||
| <<: *all_fregs | ||
| val_comb: | ||
| 'imm_val > 0': 0 | ||
| 'imm_val == 0': 0 | ||
| abstract_comb: | ||
| 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 | ||
| 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 | ||
| 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,65 @@ | ||
| c.flw: | ||
| config: | ||
| - check ISA:=regex(.*I.*F.*C.*) | ||
| mnemonics: | ||
| c.flw: 0 | ||
| rs1: | ||
| <<: *c_regs | ||
| rd: | ||
| <<: *c_fregs | ||
| val_comb: | ||
| 'imm_val > 0 and fcsr == 0': 0 | ||
| 'imm_val == 0 and fcsr == 0': 0 | ||
| abstract_comb: | ||
| 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 | ||
| 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 | ||
| 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 | ||
|
|
||
| c.flwsp: | ||
| config: | ||
| - check ISA:=regex(.*I.*F.*C.*) | ||
| opcode: | ||
| c.flwsp: 0 | ||
| rd: | ||
| <<: *c_fregs | ||
| val_comb: | ||
| 'imm_val > 0 and fcsr == 0': 0 | ||
| 'imm_val == 0 and fcsr == 0': 0 | ||
| abstract_comb: | ||
| 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 | ||
| 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 | ||
| 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 | ||
|
|
||
| c.fsw: | ||
| config: | ||
| - check ISA:=regex(.*I.*F.*C.*) | ||
| opcode: | ||
| c.fsw: 0 | ||
| rs1: | ||
| <<: *c_regs | ||
| rs2: | ||
| <<: *c_fregs | ||
| op_comb: | ||
| 'rs1 != rs2': 0 | ||
| val_comb: | ||
| 'imm_val > 0': 0 | ||
| 'imm_val == 0': 0 | ||
| abstract_comb: | ||
| 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 | ||
| 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 | ||
| 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 | ||
|
|
||
| c.fswsp: | ||
| config: | ||
| - check ISA:=regex(.*I.*F.*C.*) | ||
| opcode: | ||
| c.fswsp: 0 | ||
| rs2: | ||
| <<: *c_fregs | ||
| val_comb: | ||
| 'imm_val > 0': 0 | ||
| 'imm_val == 0': 0 | ||
| abstract_comb: | ||
| 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 | ||
| 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 | ||
| 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,188 @@ | ||
| # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore | ||
|
|
||
| fadd_b1: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b1(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b2: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b2(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b3: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b3(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b4: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b4(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b5: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b5(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b7: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b7(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b8: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b8(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b10: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b10(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b11: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b11(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b12: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b12(flen,16, "fadd.h", 2,True)': 0 | ||
|
|
||
| fadd_b13: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fadd.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rs2: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| op_comb: | ||
| <<: *rfmt_op_comb | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b13(flen,16, "fadd.h", 2,True)': 0 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,15 @@ | ||
| # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore | ||
|
|
||
| fclass_b1: | ||
| config: | ||
| - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) | ||
| opcode: | ||
| fclass.h: 0 | ||
| rs1: | ||
| <<: *all_regs | ||
| rd: | ||
| <<: *all_regs | ||
| val_comb: | ||
| abstract_comb: | ||
| 'ibm_b1(flen,16, "fclass.h", 1,True)': 0 | ||
|
|
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