tests and covergroups for the combination of mprv and sum bit added

riscv-non-isa · Dec 4, 2024 · bb63582 · allenjbaum · Jan 3, 2025 · allenjbaum
1 parent 478a3b4
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diff --git a/coverage/sv32/rv32_vm_sv32.cgf b/coverage/sv32/rv32_vm_sv32.cgf
@@ -118,7 +118,7 @@ misaligned_superpage:
     'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("ADRWXV", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0
     'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0
 
-# If MVPV bit is set, then make the exec. readable and just give a store page fault else give both load and store page fault
+# If MVPV bit is set, then do page table walk in machine mode for loads and stores.
 MPRV_bit:
   config:
     - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
@@ -340,4 +340,25 @@ reserved_rsw_pte_perm:
     '((satp) & 0x003FFFFF)  == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0
   val_comb:
     'mode == {"S", "U"} and get_pte_prop("RWXAD",   dptw1cont) ==  1 and dptw0cont == None': 0
-    'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXAD",   dptw0cont) ==  1': 0
+    'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXAD",   dptw0cont) ==  1': 0
+
+# If MVPV bit is set, then do page table walk in machine mode for loads and stores.
+MPRV_SUM_bit:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0
+  op_comb:
+    'mode == "M" and (satp >> 31) ==  ${SATP_MODE_SV32}': 0
+  csr_comb:
+    '((satp) & 0x003FFFFF)  == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0
+    #check mstatus has: Case 1: MPP=S, SUM=1, MPRV=1 Case 2: MPP=S, SUM=0, MPRV=1
+    mstatus == {0x00060800, 0x00020800}: 0       
+  val_comb:
+    'mode == "M" and mnemonic == {"lw", "sw"} and old_csr_val("mstatus") == {0x00060800, 0x00020800} and get_pte_prop("ADURWXV",   dptw1cont) ==  1 and dptw0cont == None': 0
+    'mode == "M" and mnemonic == {"lw", "sw"} and old_csr_val("mstatus") == {0x00060800, 0x00020800} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("ADURWXV",  dptw0cont) ==   1': 0
+    #Fault Checks
+    'mode == "M" and old_csr_val("mstatus") == 0x00060800 and get_pte_prop("ADURWXV",   dptw1cont) ==  1 and dptw0cont == None and len_dptw == 1': 0
+    'mode == "M" and old_csr_val("mstatus") == 0x00060800 and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("ADURWXV",  dptw0cont) == 1 and len_dptw == 2': 0
+    'mode == "M" and old_csr_val("mstatus") == 0x00020800 and get_pte_prop("ADURWXV",   dptw1cont) ==  1 and dptw0cont == None and mcause == {${CAUSE_LOAD_PAGE_FAULT}, ${CAUSE_STORE_PAGE_FAULT}}': 0
+    'mode == "M" and old_csr_val("mstatus") == 0x00020800 and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("ADURWXV",  dptw0cont) == 1 and mcause == {${CAUSE_LOAD_PAGE_FAULT}, ${CAUSE_STORE_PAGE_FAULT}}': 0
diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h
@@ -1374,6 +1374,11 @@ vmem_adj_\__MODE__\()epc:
         add     T4, T4, sp              /* calc address of correct sv_area      */
         csrr    T2, CSR_XEPC            /* T4 now pts to trapping sv_area mode  */
 
+#ifdef SKIP_MEPC
+        addi T3, T3, 0
+        j adj_\__MODE__\()epc
+#endif
+
         LREG    T3, vmem_bgn_off(T4)            // see if epc is in the vmem area
         LREG    T6, vmem_seg_siz(T4)
         add     T6, T6, T3                      // construct vmem seg end
@@ -1421,6 +1426,11 @@ adj_\__MODE__\()epc_rtn:                // adj mepc so there is at least 4B of p
 
         csrr    T2, CSR_XTVAL
 
+#ifdef SKIP_MTVAL
+        addi T3, T3, 0
+        j adj_\__MODE__\()tval
+#endif
+
 chk_\__MODE__\()tval:
         andi    T5, T5, EXCPT_CAUSE_MSK // ensures shift amt will be within range
         LI(     T3, SET_REL_TVAL_MSK)   // now check if code or data (or sig) region adjustment

diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S
@@ -0,0 +1,309 @@
+// ----------------------------------------------------------------------------------------------------------------------
+// This test is part of the test plan for the SV-32-based Virtual Memory System, available at:
+// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0
+// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid
+// ----------------------------------------------------------------------------------------------------------------------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// ----------------------------------------------------------------------------------------------------------------------
+// Test Explanation:
+// RISC-V Privileged Architecture ISA Manual -- Section 10.3
+// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support.
+// Future updates will align with ISA version 1.13.
+// 
+// Test cases are as follows:
+// ----------------------------------------------------------------------------------------------------------------------
+// ------------------------------------------MPRV test with the combination of SUM set in mstatus in M Mode (with U bit perms)---------------------------------------------------
+// 1. PTE has RWX Permissions at Level 1(Read, write, execute page) and MPRV bit set in mstatus and SUM bit is not SET:
+//		Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful.
+// 2. PTE has RWX Permissions at Level 0(Read, write, execute page) and MPRV bit set in mstatus:
+//		Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful.
+
+// Total Expected Faults :: 0
+//-------------------------------------------------------------------------------------------------------------------
+
+#define SKIP_MTVAL
+#define SKIP_MEPC
+
+#include "model_test.h"
+
+#include "arch_test.h"
+
+RVTEST_ISA("RV32I_Zicsr")
+
+# Test code region
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_SUM_bit)
+
+RVTEST_SIGBASE( x13,signature_x13_1)
+# ---------------------------------------------------------------------------------------------
+// Test the RWX permissions
+.macro VERIFICATION_RWX ADDRESS, level, VM_MODE
+   	LA(a5, \ADDRESS)														// Fetch the address to be checked
+	addi a2, a2, 16															// 16 stored in a2 for starting point
+
+	// Check store on the address.
+    sfence.vma
+	sw	a2, 20(a5)
+	SREG a2, 0(s11)
+	nop
+	addi s11, s11, REGWIDTH
+
+	#Set the required mstatus values for this test (in case of a trap)
+	SET_REQ_MSTATUS_VAL
+
+	sfence.vma
+	lw	a4, 20(a5)															// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	SREG a4, 0(s11)
+	nop
+	addi s11, s11, REGWIDTH
+
+	//check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions
+	//else jump to the end of the 4MB page to check the permissions
+    // Check if level is equal to zero (4KB page)
+	addi a2, a2, 16															// update the counter for execute
+    LI( t1, \level)
+    beqz t1, 1f  // Forward reference to avoid label redefinition
+
+    // 4MB - 4 = 4,194,300 bytes
+	// Access the last four bytes which contain the jr instruction
+    LI (t0, (0x400000 - 4))
+	.if \VM_MODE == Mmode
+	   	LA(a5, rvtest_data_1_l1)														// Fetch the address to be checked
+	.endif
+	srli a5, a5, 22
+	slli a5, a5, 22															//Clear the lower 21 bits -- offset bits(10) + level 0 bits(12)
+    add t0, a5, t0
+    jalr ra, t0, 0
+	SREG a2, 0(s11)
+	nop
+	addi s11, s11, REGWIDTH
+    j 2f
+
+1:  // 4KB - 4 = 4,092 bytes
+    LI (t0, (0x1000-4))
+	.if \VM_MODE == Mmode
+	   	LA(a5, rvtest_data_1_l0)														// Fetch the address to be checked
+	.endif
+	srli a5, a5, 12
+	slli a5, a5, 12
+    add t0, a5, t0
+    jalr ra, t0, 0
+	SREG a2, 0(s11)
+	nop
+	addi s11, s11, REGWIDTH
+
+2:  // end_macro
+    // execution test sig update
+	nop
+.endm
+
+.macro TEST_CASES_RUNNER LOWER_MODE, VA, level
+    .if \LOWER_MODE == Mmode
+		SET_REQ_MSTATUS_VAL
+    .else
+        RVTEST_GOTO_LOWER_MODE \LOWER_MODE   // Switch to the specified lower mode
+    .endif
+
+	.align 2
+
+	//JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP)
+	VERIFICATION_RWX	\VA, \level, \LOWER_MODE
+	nop
+	nop
+
+	RVTEST_GOTO_MMODE		                                        		// Switching back to M mode
+
+.endm
+
+.macro SET_REQ_MSTATUS_VAL
+		LI (s7, MSTATUS_MPRV)           
+		csrs mstatus,s7                 
+		LI (s7, MSTATUS_SUM)	//SET the MSTATUS sum bit
+		csrs mstatus,s7                 
+		LI (s7, 0x1800)	//clear previous mode
+		csrc mstatus,s7                 
+		LI (s7, 0x800)	//Smode
+		csrs mstatus,s7                 
+.endm
+
+main:
+#ifdef rvtest_mtrap_routine					                				// Verification of existance of rvtest_mtrap_routine
+	LI a4, 0xceed
+	RVTEST_SIGUPD(x13,a4)
+#endif
+#ifdef rvtest_strap_routine					                				// Verification of existance of rvtest_strap_routine
+	LI a4, 0xbeed
+	RVTEST_SIGUPD(x13,a4)
+#endif
+
+	ALL_MEM_PMP          		                  	                      	// set the PMP permissions for the whole memory
+	csrw satp, zero  		                                        		// write satp with all zeros (bare mode)
+
+//---------------------------------------------------------------------------------------------------------------------------------
+//								Virtual addresses definition section for the code, data, sig, vmem, test sections
+//---------------------------------------------------------------------------------------------------------------------------------
+
+	// test section VAs
+	.set va_data,          0x91400000                                  		// virtual address of rvtest_data_1_l1 and rvtest_data_1_l0
+	.set va_return_page_l1,     0x91800000                                  // virtual address of return_page for the rvtest_data_1_l1
+	.set va_return_page_l0,     0x91401000                                  // virtual address of return_page for the rvtest_data_1_l0
+
+	// code, data, sig, vmem section VAs
+	.set va_rvtest_code_begin,  0x9000036c                             		// virtual address of rvtest_code_begin
+	.set va_rvtest_data_begin, 	0x910003fc									// virtual address of rvtest_data_begin (for save area)
+	.set va_rvtest_sig_begin,   0x93014510                                  // virtual address of signature_x13_1
+	.set  va_rvtest_vmem_begin, 0x940003F0									// virtual address of rvtest_vmem_begin
+
+//													PTE setup for Code Region
+	PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1)
+	sfence.vma
+//													PTE setup for Data Region
+	PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1)
+	sfence.vma
+//													PTE setup for Signature Region
+	PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1)
+	PTE_SETUP_RV32_New(rvtest_sig_begin,  (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0)
+	sfence.vma
+//								register setup for the signature save in virtualization mode
+	LI (t0, va_rvtest_sig_begin)                                                       
+	LA (t1, rvtest_sig_begin)                                                      
+	sub t0, t0, t1 					        								// (VA-PA) Note: VA > PA 
+	add s11, x13, t0				        								// Translation of Signature reg
+
+//---------------------------------------------------------------------------------------------------------------------------------
+//													Save area logic
+//---------------------------------------------------------------------------------------------------------------------------------
+	LI (t0, va_rvtest_data_begin) 
+	LA (t1, rvtest_data_begin) 
+	sub t0, t0, t1         
+	addi t3, t0, sv_area_sz
+	csrr sp, mscratch      
+	add t1,sp,t3           
+	csrw sscratch, t1      
+	csrr sp, mscratch
+
+	//save area setup for code region
+	SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code)
+	//save area setup for data region
+	SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data)
+	//save area setup for sig region
+	SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig)	
+	//save area setup for vmem region
+	SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem)
+
+//---------------------------------------------------------------------------------------------------------------------------------
+//												Test Cases Start from here
+//---------------------------------------------------------------------------------------------------------------------------------
+
+	SATP_SETUP_SV32                                                         // set the SATP for virtualization
+	sfence.vma                                                              // flush the TLB
+
+//---------------------------------------------------------------------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------------------------------------------
+//													TESTS AT LEVEL 1
+//---------------------------------------------------------------------------------------------------------------------------------
+//					4MB PAGE	Region 1 under test at level 1 -- RWX permissions given to the region
+//---------------------------------------------------------------------------------------------------------------------------------
+	// Test case 1: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault 
+	PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R| PTE_V), va_data, LEVEL1)
+	sfence.vma
+
+	//return page PTE
+	PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1)
+	sfence.vma
+
+	TEST_CASES_RUNNER Mmode, va_data, LEVEL1
+
+//---------------------------------------------------------------------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------------------------------------------
+//													TESTS AT LEVEL 0
+//---------------------------------------------------------------------------------------------------------------------------------
+//					4MB PAGE	Region 1 under test at level 0 -- RWX permissions given to the region
+//---------------------------------------------------------------------------------------------------------------------------------
+	// Test case 2: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault
+	PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1)
+	PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0)
+	sfence.vma
+
+	//return page PTE
+	PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1)
+	PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0)
+	sfence.vma
+
+	TEST_CASES_RUNNER Mmode, va_data, LEVEL0
+
+
+
+#endif
+//---------------------------------------------------------------------------------------------------------------------------------
+RVTEST_CODE_END
+RVMODEL_HALT
+RVTEST_DATA_BEGIN
+.align 22
+
+//---------------------------------------------------------------------------------------------------------------------------------
+//											PHYSICAL ADDRESS REGIONS FOR TESTING
+//---------------------------------------------------------------------------------------------------------------------------------
+//Physical Address region under testing for LEVEL 1 -- Aligned by 22
+rvtest_data_1_l1:
+	nop																		//nops are added so if there is a trap
+	addi ra, ra, REGWIDTH
+	jr ra																	// return back if the access fault
+	nop
+	.word 0xbeefcaf1														// Random word
+	.word 0xbeefcaf2														// Random word
+	.rept ((1 << 20) - 7)													// (2^22 - 7) nops
+    nop
+	.endr
+	jr ra																	// return back if successful access
+
+//Physical Address region under testing for LEVEL 0 -- Aligned by 10
+rvtest_data_1_l0:
+	nop																		// trap return back skip
+	addi ra, ra, REGWIDTH
+	jr ra																	//jump back for the trap on level 1
+	nop
+	.word 0xbeefcaf1														// Random word
+	.word 0xbeefcaf2														// Random word
+	.rept ((1 << 10) - 7)													// (2^12 - 7) nops
+    nop
+	.endr
+	jr ra
+
+//---------------------------------------------------------------------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------------------------------------------
+
+#ifdef rvtest_strap_routine
+.align 12                       //complete the 4KB permission memory range
+rvtest_slvl1_pg_tbl:
+		RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G)
+#endif
+
+RVTEST_DATA_END                               
+.align 12
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+// test signatures initialization
+signature_x13_1:
+    .fill 128*(XLEN/32),4,0xcafebeef
+
+// trap signatures initialization
+#ifdef rvtest_mtrap_routine
+mtrap_sigptr:
+    .fill 128*(XLEN/32),4,0xdeadbeef
+#endif
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END