riscv-non-isa · allenjbaum · Nov 15, 2023 · Oct 25, 2023 · Oct 31, 2023
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,4 +1,7 @@
 # CHANGELOG
+## [3.8.2] - 2023-11-14
+- Added "most negative number divided by -1" case for RV64IM and RV32IM in remw, divw, div and rem tests
+
 ## [3.8.1] - 2023-11-01
 - Updated trap handler to avoid using mstatush when used for Priv Arch 1.11
 - Updated GOTO_Lower_Mode macro to adjust the save area when switching to Umode.

diff --git a/riscv-test-suite/rv32i_m/M/src/div-01.S b/riscv-test-suite/rv32i_m/M/src/div-01.S
diff --git a/riscv-test-suite/rv32i_m/M/src/divu-01.S b/riscv-test-suite/rv32i_m/M/src/divu-01.S
diff --git a/riscv-test-suite/rv32i_m/M/src/mul-01.S b/riscv-test-suite/rv32i_m/M/src/mul-01.S
diff --git a/riscv-test-suite/rv32i_m/M/src/mulh-01.S b/riscv-test-suite/rv32i_m/M/src/mulh-01.S
diff --git a/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S b/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S
diff --git a/riscv-test-suite/rv32i_m/M/src/mulhu-01.S b/riscv-test-suite/rv32i_m/M/src/mulhu-01.S
diff --git a/riscv-test-suite/rv32i_m/M/src/rem-01.S b/riscv-test-suite/rv32i_m/M/src/rem-01.S
diff --git a/riscv-test-suite/rv32i_m/M/src/remu-01.S b/riscv-test-suite/rv32i_m/M/src/remu-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/div-01.S b/riscv-test-suite/rv64i_m/M/src/div-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/divu-01.S b/riscv-test-suite/rv64i_m/M/src/divu-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/divuw-01.S b/riscv-test-suite/rv64i_m/M/src/divuw-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/divw-01.S b/riscv-test-suite/rv64i_m/M/src/divw-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/mul-01.S b/riscv-test-suite/rv64i_m/M/src/mul-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/mulh-01.S b/riscv-test-suite/rv64i_m/M/src/mulh-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S b/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/mulhu-01.S b/riscv-test-suite/rv64i_m/M/src/mulhu-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/mulw-01.S b/riscv-test-suite/rv64i_m/M/src/mulw-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/rem-01.S b/riscv-test-suite/rv64i_m/M/src/rem-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/remu-01.S b/riscv-test-suite/rv64i_m/M/src/remu-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/remuw-01.S b/riscv-test-suite/rv64i_m/M/src/remuw-01.S
diff --git a/riscv-test-suite/rv64i_m/M/src/remw-01.S b/riscv-test-suite/rv64i_m/M/src/remw-01.S