Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Add m-mode, s-mode interrupt test cases using test_model.h MSW and MTIMER clint macros. #435

Open
wants to merge 9 commits into
base: dev
Choose a base branch
from
Open

Add m-mode, s-mode interrupt test cases using test_model.h MSW and MTIMER clint macros. #435

wants to merge 9 commits into from

Commits on Feb 6, 2024

  1. Add m-mode interrupt test-cases using clint method of interrupt gener… 

    …ation

M-mode interrupt test-cases using msw and mtimer clint interrupts

Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers
    dansmathers authored Feb 6, 2024
    Configuration menu
    Copy the full SHA
    0955909 View commit details
    Browse the repository at this point in the history

  2. Delete riscv-test-suite/rv32i_m/Smclint directory 

    Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers
    dansmathers authored Feb 6, 2024
    Configuration menu
    Copy the full SHA
    80ce4c4 View commit details
    Browse the repository at this point in the history

  3. ADD smclint testcase summary 

    Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers
    dansmathers authored Feb 6, 2024
    Configuration menu
    Copy the full SHA
    f815ebf View commit details
    Browse the repository at this point in the history

  4. Add interrupt test cases using clint MSW and MTIMER interrupts 

    requires 
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106

To include these tests in riscof testlist flow, add Smclint to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclint



Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers
    dansmathers authored Feb 6, 2024
    Configuration menu
    Copy the full SHA
    6642c22 View commit details
    Browse the repository at this point in the history

  5. coverage for 

    Coverage checks mcause.int to verify if an interrupt occurred

Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers
    dansmathers authored Feb 6, 2024
    Configuration menu
    Copy the full SHA
    be99baa View commit details
    Browse the repository at this point in the history

  6. Update encoding.h to match latest spike version 

    Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers
    dansmathers authored Feb 6, 2024
    Configuration menu
    Copy the full SHA
    f6000f9 View commit details
    Browse the repository at this point in the history

  7. Add s-mode interrupt testcases using clint interrupt generation 

    Description of s-mode interrupt testcases

Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers
    dansmathers authored Feb 6, 2024
    Configuration menu
    Copy the full SHA
    094d581 View commit details
    Browse the repository at this point in the history

  8. s-mode interrupt testcases using CLINT method to generate interrupts 

    s-mode interrupt testcases by delegating CLINT MSW/MTIMER interrupts

Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers
    dansmathers authored Feb 6, 2024
    Configuration menu
    Copy the full SHA
    832132b View commit details
    Browse the repository at this point in the history

  9. ssclint coverage file 

    Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers
    dansmathers authored Feb 6, 2024
    Configuration menu
    Copy the full SHA
    efd3d22 View commit details
    Browse the repository at this point in the history