Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Atomic extension LR/SC tests and coverpoints #439

Open
wants to merge 5 commits into
base: dev
Choose a base branch
from
Open

Atomic extension LR/SC tests and coverpoints #439

Show file tree
Hide file tree
Changes from 3 commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
5524fb5
Coverpoints for lr-sc added for 32 and 64 bit architecture
MuhammadHammad001 Feb 21, 2024
27a9cc4
Added tests for LR/SC instructions of A extension for RV32 and RV64
maarij-10xe Feb 22, 2024
7925ef0
Update CHANGELOG.md
maarij-10xe Feb 26, 2024
2d18ca6
Merge branch 'dev' into atomic-extension-lr-sc-tests-coverpoints
jamesbeyond Jun 6, 2024
27ed01d
Merge branch 'dev' into atomic-extension-lr-sc-tests-coverpoints
jamesbeyond Jul 2, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions CHANGELOG.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,8 @@
# CHANGELOG

## [3.8.10] -- 2024-02-21
- Adds tests for LR/SC instructions in Atomic (A) Extension.

## [3.8.9] -- 2024-01-12
- Fixed Check ISA fields to include 32/64 in Zicond tests. Note that the riscv-ctg CGFs have not been updated.

Expand Down
211 changes: 211 additions & 0 deletions coverage/rv_lr_sc_64.cgf
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,211 @@
#For lr-sc-01.S
lr-sc-01:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq != 0x1": 0 #no aq flag used
"mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used
val_comb:
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val: 0
mnemonic == 'sc.d' and rs2_val == get_mem_val(rs1_val, 8) and rd_val == 0: 0

#For lr-sc-fail-01.S
lr-sc-fail-01:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq != 0x1": 0 #no aq flag used
"mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used
val_comb:
#reservation successfull
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val: 0
#rd -> non-zero on sc
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs1_val and rd_val!=0: 0

#For lr-sc-fail-02.S
lr-sc-fail-02:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq != 0x1": 0 #no aq flag used
"mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used
val_comb:
#reservation successfull - it should hit 4 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#rd -> 1 on sc -- it should hit 8 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs2_val and rd_val!=0: 0

#For lr-sc-sw.S
lr-sc-sw:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
sw: 0
op_comb:
"mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used
"mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used
val_comb:
#reservation successfull - it should hit 2 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#check store word successfull? imm_val is zero.
mnemonic == 'sw' and get_mem_val(rs1_val, 8) == rs2_val : 0
#rd -> 0 on sc -- it should hit 2 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0

#For lr-aq-sc-01.S
lr-aq-sc-01:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used
"mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used
val_comb:
#reservation successfull - it should hit 4 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#rd -> 0 on sc -- it should hit 4 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0

#For lr-aq-sc-rl-01.S
lr-aq-sc-rl-01:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used
"mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used
val_comb:
#reservation successfull - it should hit 4 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#rd -> 0 on sc -- it should hit 4 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0

#For lr-sc-constrained-loop-01.S
lr-sc-constrained-loop-01:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used
"mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used
val_comb:
#reservation successfull - it should hit 1 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#rd -> 0 on sc -- it should hit 1 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0

#For lr-sc-constrained-loop-02.S
lr-sc-constrained-loop-02:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and rs1 == 'x31' and aq == 0x1": 0 #aq flag used
"mnemonic == 'sc.d' and rs1 == 'x26' and rl == 0x1": 0 #rl flag used for some other register
val_comb:
#reservation successfull - it should hit 4 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#rd -> 1 on sc -- it should hit 4 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs2_val and rd_val!=0: 0

#For lr-sc-constrained-loop-03.S
lr-sc-constrained-loop-03:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used
"mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used
val_comb:
#reservation successfull - it should hit 1 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#rd -> 1 on sc -- it should hit 1 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0

#For lr-sc-constrained-loop-04.S
lr-sc-constrained-loop-04:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used
"mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used
val_comb:
#reservation successfull - it should hit 1 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#rd -> 1 on sc -- it should hit 4 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs2_val and rd_val!=0: 0

#For lr-sc-unconstrained-loop-01.S
lr-sc-unconstrained-loop-01:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used
"mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used
val_comb:
#reservation successfull - it should hit 2 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#rd -> 0 on sc -- it should hit 2 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0

#For lr-sc-rl-01.S
lr-sc-rl-01:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq == 0x0": 0 #no aq flag used
"mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used
val_comb:
#reservation successfull - it should hit 4 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0
#rd -> 0 on sc -- it should hit 4 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0

#For lr-sc-misaligned-01.S
lr-sc-misaligned-01:
config:
- check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True;
mnemonics:
lr.d: 0
sc.d: 0
op_comb:
"mnemonic == 'lr.d' and aq == 0x0": 0 #no aq flag used
"mnemonic == 'sc.d' and rl == 0x0": 0 #no rl flag used
csr_comb:
#misaligned store/amo fault -- it should hit 3 times
mcause == 0x06: 0
val_comb:
#reservation failed - it should hit 3 times
mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) != rd_val : 0
#rd -> 1 on sc -- it should hit 3 times
mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs2_val and rd_val!=0: 0
Loading