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Physical Memory Protection (32/64) Tests and Covergroups #462

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Nov 4, 2024
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095f7ef
PMP32 and PMP64 Covergroups added
MuhammadHammad001 Apr 29, 2024
5a44a3f
YAML basedHeaders/Macros file for the coverpoints added
MuhammadHammad001 Apr 29, 2024
dfcad6b
Added PMP32 and PMP64 ACTs
UmerShahidengr Apr 29, 2024
6ecb0ef
Added Changelog entry
UmerShahidengr Apr 29, 2024
05f23bb
PMP Macros added in Header file, PMP tests updated to support byte an…
MuhammadHammad001 Jul 2, 2024
d5a1e8e
64 bit PMP Tests and coverpoints updated
MuhammadHammad001 Jul 2, 2024
1214bb0
32 bit PMP Coverpoints updated to more compact version
MuhammadHammad001 Jul 2, 2024
a0bc569
Merge branch 'dev' into pmp_cov_test
MuhammadHammad001 Jul 2, 2024
65cb741
Changelog entry removed for the PMP Tests and Coverpoints
MuhammadHammad001 Jul 18, 2024
a460920
Merge branch 'dev' into pmp_cov_test
UmerShahidengr Jul 23, 2024
bb318a9
Update rv32_pmp.cgf
UmerShahidengr Aug 2, 2024
a4ed357
Merge branch 'dev' into pmp_cov_test
UmerShahidengr Aug 2, 2024
ccfa08f
Update rv64_pmp.cgf
UmerShahidengr Aug 2, 2024
4650b89
Merge branch 'dev' into pmp_cov_test
jamesbeyond Oct 7, 2024
408b032
Merge branch 'dev' into pmp_cov_test
UmerShahidengr Oct 9, 2024
9c5341e
Merge branch 'dev' into pmp_cov_test
UmerShahidengr Oct 15, 2024
112ed98
Merge branch 'riscv-non-isa:dev' into pmp_cov_test
UmerShahidengr Oct 18, 2024
a48e1ef
Merge branch 'dev' into pmp_cov_test
UmerShahidengr Oct 18, 2024
21489f3
Merge branch 'riscv-non-isa:dev' into pmp_cov_test
UmerShahidengr Oct 18, 2024
304f853
Changed the CI to see the artifacts
UmerShahidengr Oct 18, 2024
7695c7c
Reverted the change in CI
UmerShahidengr Oct 18, 2024
c068f3c
Merge branch 'dev' into pmp_cov_test
UmerShahidengr Oct 25, 2024
1be1bcb
Removed __pycache__ folders
UmerShahidengr Oct 25, 2024
4a42f28
removed riscof work folder
MuhammadHammad001 Oct 26, 2024
7954b57
RISCOF work folder in rv64 removed
MuhammadHammad001 Oct 26, 2024
043effc
Merge branch 'dev' into pmp_cov_test
jamesbeyond Nov 4, 2024
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64 bit PMP Tests and coverpoints updated
  • Loading branch information
MuhammadHammad001 committed Jul 2, 2024
commit d5a1e8e9ef7e4efff159549ed38f013d0b3ad3fc
1,102 changes: 618 additions & 484 deletions coverage/rv64_pmp.cgf

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions riscv-test-suite/rv64i_m/pmp64/pmp64-CFG-reg.S
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",pmp_cfg_locked_write_unrelated)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMP_MACROS; mac PMP_helper_Coverpoints",pmp_cfg_locked_write_unrelated)
RVTEST_SIGBASE( x3,signature_x3_1)

.attribute unaligned_access, 0
Expand Down Expand Up @@ -113,7 +113,7 @@ signature_x3_1:
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
.fill 128*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

Expand Down
40 changes: 30 additions & 10 deletions riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", PMP_NA4_priority_r_level_2)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMP_MACROS; mac PMP_helper_Coverpoints", PMP_NA4_priority_r_level_2)
RVTEST_SIGBASE( x13,signature_x13_1)

.attribute unaligned_access, 0
Expand All @@ -39,17 +39,37 @@ RVTEST_SIGBASE( x13,signature_x13_1)
#define NOP 0x13
.macro VERIFICATION_RWX ADDRESS
LA(a5, \ADDRESS) // Fetch the address to be checked
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sb a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
sh a4,0(a5) // store data
nop
nop
sw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
sd a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
lb a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4) //verify that the data is stored successfuly
lh a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4)
lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
/* WRITING new value to memory region
TRAP if the WRITability is blocked */
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sd a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
nop
RVTEST_SIGUPD(x13,a4)
jal \ADDRESS // Test for execution, an instruction is placed at this address
nop
nop
jal \ADDRESS // Test for execution, an instruction is placed at this address
.endm

Expand Down Expand Up @@ -196,7 +216,7 @@ signature_x13_1:
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
.fill 128*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

Expand Down
41 changes: 31 additions & 10 deletions riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority.S
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_r)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMP_MACROS; mac PMP_helper_Coverpoints",PMP_NA4_priority_r)
RVTEST_SIGBASE( x13,signature_x13_1)
.attribute unaligned_access, 0
.attribute stack_align, 16
Expand All @@ -41,18 +41,39 @@ RVTEST_SIGBASE( x13,signature_x13_1)
#define NOP 0x13
.macro VERIFICATION_RWX ADDRESS
LA(a5, \ADDRESS) // Fetch the address to be checked
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sb a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
sh a4,0(a5) // store data
nop
nop
sw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
sd a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
lb a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4) //verify that the data is stored successfuly
lh a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4)
lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
/* WRITING new value to memory region
TRAP if the WRITability is blocked */
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sd a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
nop
RVTEST_SIGUPD(x13,a4)
jal \ADDRESS // Test for execution, an instruction is placed at this address
nop
nop
jal \ADDRESS // Test for execution, an instruction is placed at this address

.endm

main:
Expand Down Expand Up @@ -174,7 +195,7 @@ signature_x13_1:
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
.fill 128*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

Expand Down
41 changes: 31 additions & 10 deletions riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R.S
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_r)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMP_MACROS; mac PMP_helper_Coverpoints",PMP_NA4_r)
RVTEST_SIGBASE( x13,signature_x13_1)

.attribute unaligned_access, 0
Expand All @@ -43,18 +43,39 @@ RVTEST_SIGBASE( x13,signature_x13_1)
#define NOP 0x13
.macro VERIFICATION_RWX ADDRESS
LA(a5, \ADDRESS) // Fetch the address to be checked
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sb a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
sh a4,0(a5) // store data
nop
nop
sw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
sd a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
lb a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4) //verify that the data is stored successfuly
lh a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4)
lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
/* WRITING new value to memory region
TRAP if the WRITability is blocked */
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sd a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
nop
RVTEST_SIGUPD(x13,a4)
jal \ADDRESS // Test for execution, an instruction is placed at this address
nop
nop
jal \ADDRESS // Test for execution, an instruction is placed at this address

.endm

main:
Expand Down Expand Up @@ -199,7 +220,7 @@ signature_x13_1:
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
.fill 128*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

Expand Down
41 changes: 31 additions & 10 deletions riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rw_level_2)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMP_MACROS; mac PMP_helper_Coverpoints",PMP_NA4_priority_rw_level_2)
RVTEST_SIGBASE( x13,signature_x13_1)

.attribute unaligned_access, 0
Expand All @@ -39,18 +39,39 @@ RVTEST_SIGBASE( x13,signature_x13_1)
#define NOP 0x13
.macro VERIFICATION_RWX ADDRESS
LA(a5, \ADDRESS) // Fetch the address to be checked
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sb a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
sh a4,0(a5) // store data
nop
nop
sw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
sd a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
lb a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4) //verify that the data is stored successfuly
lh a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4)
lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
/* WRITING new value to memory region
TRAP if the WRITability is blocked */
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sd a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
nop
RVTEST_SIGUPD(x13,a4)
jal \ADDRESS // Test for execution, an instruction is placed at this address
nop
nop
jal \ADDRESS // Test for execution, an instruction is placed at this address

.endm

main:
Expand Down Expand Up @@ -192,7 +213,7 @@ signature_x13_1:
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
.fill 128*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

Expand Down
41 changes: 31 additions & 10 deletions riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority.S
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rw)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMP_MACROS; mac PMP_helper_Coverpoints",PMP_NA4_priority_rw)
RVTEST_SIGBASE( x13,signature_x13_1)
.attribute unaligned_access, 0
.attribute stack_align, 16
Expand All @@ -40,18 +40,39 @@ RVTEST_SIGBASE( x13,signature_x13_1)
#define NOP 0x13
.macro VERIFICATION_RWX ADDRESS
LA(a5, \ADDRESS) // Fetch the address to be checked
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sb a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
sh a4,0(a5) // store data
nop
nop
sw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
sd a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
lb a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4) //verify that the data is stored successfuly
lh a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
RVTEST_SIGUPD(x13,a4)
lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
nop
nop
/* WRITING new value to memory region
TRAP if the WRITability is blocked */
LI(a4, NOP) // Load the new value (NOP Instruction ID)
sd a4,0(a5) // Store the new value (NOT TRAP => W enabled)
nop
nop
ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
nop
RVTEST_SIGUPD(x13,a4)
jal \ADDRESS // Test for execution, an instruction is placed at this address
nop
nop
jal \ADDRESS // Test for execution, an instruction is placed at this address

.endm

main:
Expand Down Expand Up @@ -173,7 +194,7 @@ signature_x13_1:
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
.fill 128*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

Expand Down
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