Virtual Memory SV-32 Address Translation Scheme Tests and Covergroups

.github/workflows/test.yml

@@ -135,7 +135,7 @@ jobs:
       - name: Config and run riscof for RV${{ matrix.xlen }}
         run: |
           cd riscof-plugins/rv${{ matrix.xlen }}
-          riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m/ --env ../../riscv-test-suite/env
+          riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m --env ../../riscv-test-suite/env
 
       #Check the existance of the riscof work folder, and add the PATH to environment variable
       - name: Check size and determine upload path
@@ -147,8 +147,8 @@ jobs:
           if [ -d "$work_folder" ]; then
             folder_size=$(du -sm "$work_folder" | cut -f1)
             echo "Folder size: ${folder_size} MB"
-            if [ "$folder_size" -gt 1000 ]; then
-              echo "Size exceeds 1 GB. Checking if report exists."
+            if [ "$folder_size" -gt 100000 ]; then
+              echo "Size exceeds 10 GB. Checking if report exists."
               if [ -f "$report_file" ]; then
                 echo "Uploading RISCOF generated report only."
                 echo "upload_path=$report_file" >> $GITHUB_ENV
@@ -173,4 +173,4 @@ jobs:
           name: riscof-artifact-rv${{ matrix.xlen }}
           path: ${{ env.upload_path }}
           compression-level: 6
-          overwrite: true
+          overwrite: true

coverage/header_file.yaml

@@ -67,7 +67,7 @@ common:
  SATP64_ASID: 0x0FFFF00000000000
  SATP64_PPN: 0x00000FFFFFFFFFFF
  SATP_MODE_OFF: 0
- SATP_MODE_SV32: 1
+ SATP_MODE_SV32: 0x1
  SATP_MODE_SV39: 8
  SATP_MODE_SV48: 9
  SATP_MODE_SV57: 10
@@ -932,4 +932,17 @@ PMP_helper_Coverpoints:
  TOR_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))
  NA4_REGION_ADDRESS_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))
  NA4_PRIORITY_REGION_MATCH: (rs1_val + imm_val == (pmpaddr3 << 2))
- NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))
+ NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))
+
+SV32_MACROS:
+ LEVEL_1_JUMP_SIZE: (0x400000 - 4)
+ LEVEL_0_JUMP_SIZE: (0x1000-4)
+ read: "RWX"
+ writ: "rx"
+ va_data_sv32: (0x91400000)
+
+PMM_MACROS:
+ PMM_MASK: 0x300000000
+ PMM_MASK_SV57: 0x200000000
+ PMM_MASK_SV48: 0x300000000
+ PMM_MASK_DISABLED: 0x000000000

riscof-plugins/rv32/sail_cSim/env/model_test.h

@@ -1,5 +1,11 @@
 #ifndef _COMPLIANCE_MODEL_H
 #define _COMPLIANCE_MODEL_H
+#if XLEN == 64
+  #define ALIGNMENT 3
+#else
+  #define ALIGNMENT 2
+#endif
+
 
 #define RVMODEL_DATA_SECTION \
         .pushsection .tohost,"aw",@progbits;                            \
@@ -23,12 +29,13 @@ li x1, 1                ;\
 //RV_COMPLIANCE_DATA_BEGIN                                                                          
 #define RVMODEL_DATA_BEGIN		;\
 RVMODEL_DATA_SECTION			;\
-.align 4                  ;\
+.align ALIGNMENT;\
 .global begin_signature   ;\
 begin_signature:
 
 //RV_COMPLIANCE_DATA_END                                                                            
 #define RVMODEL_DATA_END                                                      \
+.align ALIGNMENT;\
 .global end_signature; end_signature:
 
 
@@ -54,4 +61,4 @@ RVMODEL_DATA_SECTION			;\
 #define RVMODEL_CLEAR_MEXT_INT
 
 
-#endif // _COMPLIANCE_MODEL_H
+#endif // _COMPLIANCE_MODEL_H

riscof-plugins/rv32/spike_simple/env/model_test.h

@@ -33,6 +33,7 @@ li x1, 1                ;\
 
 //RV_COMPLIANCE_DATA_END
 #define RVMODEL_DATA_END                                                      \
+.align ALIGNMENT;\
   .global end_signature; end_signature:  
 
 //RVTEST_IO_INIT
@@ -57,4 +58,4 @@ li x1, 1                ;\
 #define RVMODEL_CLEAR_MEXT_INT
 
 
-#endif // _COMPLIANCE_MODEL_H
+#endif // _COMPLIANCE_MODEL_H

riscv-test-suite/env/arch_test.h

@@ -1380,6 +1380,11 @@ vmem_adj_\__MODE__\()epc:
         add     T4, T4, sp              /* calc address of correct sv_area      */
         csrr    T2, CSR_XEPC            /* T4 now pts to trapping sv_area mode  */
 
+#ifdef SKIP_MEPC
+        addi T3, T3, 0
+        j adj_\__MODE__\()epc
+#endif
+
         LREG    T3, vmem_bgn_off(T4)            // see if epc is in the vmem area
         LREG    T6, vmem_seg_siz(T4)
         add     T6, T6, T3                      // construct vmem seg end
@@ -1427,6 +1432,11 @@ adj_\__MODE__\()epc_rtn:                // adj mepc so there is at least 4B of p
 
         csrr    T2, CSR_XTVAL
 
+#ifdef SKIP_MTVAL
+        addi T3, T3, 0
+        j adj_\__MODE__\()tval
+#endif
+
 chk_\__MODE__\()tval:
         andi    T5, T5, EXCPT_CAUSE_MSK // ensures shift amt will be within range
         LI(     T3, SET_REL_TVAL_MSK)   // now check if code or data (or sig) region adjustment

riscv-test-suite/env/test_macros.h

@@ -21,6 +21,8 @@
 #define LEVEL3 0x03
 #define LEVEL4 0x04
 
+#define ALL_F_S 0xFFFFFFFF
+
 #define sv39 0x00
 #define sv48 0x01
 #define sv57 0x02
@@ -189,14 +191,37 @@ Mend_PMP:                                    ;\
     or _PAR, _PAR, _PR                                            ;\
     SREG _PAR, 0(_TR1);                                          
 
-#define PTE_SETUP_SV32(_PAR, _PR, _TR0, _TR1, _VAR, level)  	  ;\
-    .if (level==1)                                                ;\
-        LA(_TR1, rvtest_Sroot_pg_tbl)                             ;\
-    .endif                                                        ;\
-    .if (level==0)                                                ;\
-        LA(_TR1, rvtest_slvl1_pg_tbl)                             ;\
-    .endif                                                        ;\
-    PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level)
+#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level)  	;\
+    srli _PAR, _PAR, 12                                         ;\
+    slli _PAR, _PAR, 10                                         ;\
+    or _PAR, _PAR, _PR                                          ;\
+    .if (level==1)                                              ;\
+        LA(_TR1, rvtest_Sroot_pg_tbl)                           ;\
+        LI(_TR0, ((VA>>22)&0x3FF)<<2)                           ;\
+    .endif                                                      ;\
+    .if (level==0)                                              ;\
+        LA(_TR1, rvtest_slvl1_pg_tbl)                           ;\
+        LI(_TR0, ((VA>>12)&0x3FF)<<2)                           ;\
+    .endif                                                      ;\
+    add _TR1, _TR1, _TR0                                        ;\
+    SREG _PAR, 0(_TR1);                                          
+
+// More Robust version of PTE_SETUP_32 to setup a PTE for a PA using Va
+// in a single line.
+//args: PA: Label of Physical Address, PERMS: permissions in hex
+//args: VA: Virtual Address in hex, level: Level to store at
+#define PTE_SETUP_RV32_New(PA_LBL, PERMS, VA, level)           ;\
+    LA(a0, PA_LBL)                                             ;\
+    LI(a1, PERMS)                                              ;\
+	PTE_SETUP_RV32(a0, a1, t0, t1, VA, level)                  ;\
+
+#define SAVE_AREA_SETUP(VA, PA_LBL, _REG_NAME)                  ;\
+	LI (t0, VA)                                                 ;\
+	LA (t1, PA_LBL)                                             ;\
+	sub t0, t0, t1                                              ;\
+	LREG t1, _REG_NAME##_bgn_off+0*sv_area_sz(sp)               ;\
+	add t2, t1, t0                                              ;\
+	SREG t2, _REG_NAME##_bgn_off+1*sv_area_sz(sp)               ;\
 
 #define PTE_SETUP_SV39(_PAR, _PR, _TR0, _TR1, _VAR, level)  	  ;\
     .if (level==2)                                                ;\

riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S

@@ -0,0 +1,130 @@
+// ----------------------------------------------------------------------------------------------------------------------
+// This test is part of the test plan for the SV-32-based Virtual Memory System, available at:
+// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0
+// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid
+// ----------------------------------------------------------------------------------------------------------------------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// ----------------------------------------------------------------------------------------------------------------------
+// Test Explanation:
+// RISC-V Privileged Architecture ISA Manual -- Section 10.3
+// 
+// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support.
+// Future updates will align with ISA version 1.13.
+// 
+// This test verifies the functionality of mstatus.TVM bit with the satp and sfence.vma
+// Test cases are as follows:
+// ----------------------------------------------------------------------------------------------------------------------
+//	1. satp and sfence.vma accessed in M Mode with mstatus.tvm bit set -> Successful
+//	2. satp and sfence.vma accessed in S Mode with mstatus.tvm bit set -> illegal instruction exception
+//
+// Total Expected Faults: 2
+// ----------------------------------------------------------------------------------------------------------------------
+
+//TODO: instead of using two different tests, use a single test for hart/software update.
+
+#include "model_test.h"
+
+#include "arch_test.h"
+
+RVTEST_ISA("RV32I_Zicsr")
+
+# Test code region
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", mstatus_tvm)
+
+RVTEST_SIGBASE( x13,signature_x13_1)
+
+main:
+#ifdef rvtest_mtrap_routine					                				// Verification of existance of rvtest_mtrap_routine
+	LI a4, 0xceed
+	RVTEST_SIGUPD(x13,a4)
+#endif
+#ifdef rvtest_strap_routine					                				// Verification of existance of rvtest_strap_routine
+	LI a4, 0xbeed
+	RVTEST_SIGUPD(x13,a4)
+#endif
+
+	ALL_MEM_PMP          		                  	                      	// set the PMP permissions for the whole memory
+	csrw satp, zero  		                                        			// write satp with all zeros (bare mode)
+
+	#set the mstatus with the TVM bit
+	LI (t4, MSTATUS_TVM)
+	csrw mstatus, t4
+	csrr t3, mstatus
+	RVTEST_SIGUPD(x13,t3)
+
+// ------------------------------------------------------------------------------------------------------------
+// 										satp access in M Mode using csrrw, csrrc, csrrs
+// ------------------------------------------------------------------------------------------------------------
+	li t0, 1																//initial value for t0 = 1
+	#successful access
+	csrw satp, t0  		                                        			// write satp with some value
+	csrr t3, satp
+	RVTEST_SIGUPD(x13,t3)
+
+	#successful access
+	sfence.vma
+	nop
+	nop
+
+// ------------------------------------------------------------------------------------------------------------
+// 										satp access in S Mode
+// ------------------------------------------------------------------------------------------------------------
+
+	RVTEST_GOTO_LOWER_MODE Smode
+
+	li t0, 1																//initial value for t0 = 1
+	csrw satp, t0  		                                        			// write satp with some value
+	nop
+	nop
+
+	sfence.vma
+	nop
+	nop
+
+	RVTEST_GOTO_MMODE		                                        		// Switching back to M mode
+
+#endif
+//---------------------------------------------------------------------------------------------------------------------------------
+RVTEST_CODE_END
+RVMODEL_HALT
+RVTEST_DATA_BEGIN
+.align 22
+
+//---------------------------------------------------------------------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------------------------------------------
+
+#ifdef rvtest_strap_routine
+.align 12                       //complete the 4KB permission memory range
+rvtest_slvl1_pg_tbl:
+		RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G)
+#endif
+
+RVTEST_DATA_END                
+.align 12
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+// test signatures initialization
+signature_x13_1:
+    .fill 64*(XLEN/32),4,0xcafebeef
+
+// trap signatures initialization
+#ifdef rvtest_mtrap_routine
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+#endif
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END