Commits on Oct 26, 2023

1. Relax GOT indirection into PC-relative addressing …

   Some psABIs define the linker optimizations to relax a GOT load into a
   PC-relative address materialization. AArch64 [1] allows the linker to
   rewrite ADRP+ADD into ADR. x86-64 does the same thing with the
   `R_X86_64_GOTPCRELX` and `R_X86_64_REX_GOTPCRELX` relocations.
   
   In our case, we have lots of AUIPC+LD instruction pairs to load an
   address from the GOT in our RISC-V programs because `la` assembly pseudo
   instruction is expanded to that instruction pair. If the PC-relative
   address loaded by the instruction pair is a link-time constant, we can
   rewrite the instructions with AUIPC+ADDI to directly materialize the
   value into a register, which eliminates one memory load.
   
   [1] https://github.com/ARM-software/abi-aa/blob/844a79fd4c77252a11342709e3b27b2c9f590cf1/aaelf64/aaelf64.rst#relocation-optimization

   

   rui314 committed Oct 26, 2023
   Configuration menu

   • View commit details
   • Copy full SHA for 1a91124
   • Browse repository at this point

   Copy the full SHA

   1a91124 View commit details

   Browse the repository at this point in the history