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Add RISC-V hart reqs and tests over from server soc spec.
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As per mailing list discussion and agreement between Greg and Ved, these will move from the Server SoC spec.

Signed-off-by: Andrei Warkentin <[email protected]>
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andreiw committed Dec 5, 2023
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51 changes: 28 additions & 23 deletions server_platform.bib
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@electronic{ACPI,
title = {Advanced Configuration and Power Interface (ACPI) Specification},
url = {https://uefi.org/specifications}
}
@electronic{AHCI,
title = {Advanced Host Controller Interface (AHCI)},
url = {https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-spec-rev1-3-1.pdf},
year = {}
}
@electronic{BRS,
title = {RISC-V Boot and Runtime Services Specification},
url = {https://github.com/riscv-non-isa/riscv-brs},
Expand All @@ -8,6 +17,25 @@ @electronic{BRSTest
url = {https://github.com/riscv-non-isa/riscv-brs},
year = {}
}
@electronic{NS16550,
title = {National Semiconductor PC16550D UART Datasheet},
url = {https://www.scs.stanford.edu/10wi-cs140/pintos/specs/pc16550d.pdf},
year = {}
}
@electronic{PCI,
title = {PCI Express® Base Specification Revision 6.0},
url = {https://pcisig.com/pci-express-6.0-specification},
year = {}
}
@electronic{RFC_2119,
title = {Key words for use in RFCs to Indicate Requirement Levels},
url = {https://datatracker.ietf.org/doc/html/rfc2119}
}
@electronic{RVA23,
title = {RVA23 Profiles},
url = {https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc},
year = {}
}
@electronic{ServerSoC,
title = {RISC-V Server SoC Specification},
url = {https://github.com/riscv-non-isa/server-soc},
Expand All @@ -18,35 +46,12 @@ @electronic{ServerSoCTest
url = {https://github.com/riscv-non-isa/server-soc},
year = {}
}
@electronic{RFC_2119,
title = {Key words for use in RFCs to Indicate Requirement Levels},
url = {https://datatracker.ietf.org/doc/html/rfc2119}
}
@electronic{ACPI,
title = {Advanced Configuration and Power Interface (ACPI) Specification},
url = {https://uefi.org/specifications}
}
@electronic{UEFI,
title = {Unified Extensible Firmware Interface},
url = {https://uefi.org/specifications}
}
@electronic{PCI,
title = {PCI Express® Base Specification Revision 6.0},
url = {https://pcisig.com/pci-express-6.0-specification},
year = {}
}
@electronic{NS16550,
title = {National Semiconductor PC16550D UART Datasheet},
url = {https://www.scs.stanford.edu/10wi-cs140/pintos/specs/pc16550d.pdf},
year = {}
}
@electronic{XHCI,
title = {eXtensible Host Controller Interface for Universal Serial Bus 1.2},
url = {https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf},
year = {}
}
@electronic{AHCI,
title = {Advanced Host Controller Interface (AHCI)},
url = {https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-spec-rev1-3-1.pdf},
year = {}
}
45 changes: 23 additions & 22 deletions server_platform_intro.adoc
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Expand Up @@ -21,21 +21,22 @@ computing systems that may be used for one or more of these purposes.
.Components of a RISC-V Server Platform
image::riscv-server-platform.png[width=800]

The RISC-V server platform is defined as the collection of SoC hardware,
peripherals, platform firmware, boot/runtime services, and platform security services.
The platform provides hardware interfaces (e.g., harts, timers, interrupt
controllers, PCIe root ports, etc.) to portable system software. It also offers a set of
standardized boot and runtime services based on the UEFI and ACPI standards. To
support provisioning and platform management, it interfaces with a baseboard
management controller (BMC) through both in-band and out-of-band (OOB)
management interfaces. The in-band management interfaces support the use of
standard manageability specifications like MCTP, PLDM, IPMI, and Redfish for
provisioning and management of the operating system executing on the platform.
The OOB interface supports the use of standard manageability specifications like
MCTP, PLDM, Redfish, and IPMI for functions such as power management, telemetry,
debug, and provisioning. The platform security model includes guidelines and requirements
for aspects such as debug authorization, secure/measured boot, firmware updates,
firmware resilience, and confidential computing, among others.
The RISC-V server platform is defined as the collection of RVA profile-compliant
application processor harts, SoC hardware, peripherals, platform firmware,
boot/runtime services, and platform security services. The platform provides
hardware interfaces (e.g., harts, timers, interrupt controllers, PCIe root ports, etc.)
to portable system software. It also offers a set of standardized boot and runtime
services based on the UEFI and ACPI standards. To support provisioning and
platform management, it interfaces with a baseboard management controller (BMC)
through both in-band and out-of-band (OOB) management interfaces. The in-band
management interfaces support the use of standard manageability specifications
like MCTP, PLDM, IPMI, and Redfish for provisioning and management of the operating
system executing on the platform. The OOB interface supports the use of standard
manageability specifications like MCTP, PLDM, Redfish, and IPMI for functions such
as power management, telemetry, debug, and provisioning. The platform security model
includes guidelines and requirements for aspects such as debug authorization,
secure/measured boot, firmware updates, firmware resilience, and confidential
computing, among others.

The platform firmware, typically operating at privilege level M, is
considered part of the platform and is usually expected to be customized and
Expand All @@ -45,13 +46,13 @@ and platform security.

This specification standardizes the requirements for hardware and software
interfaces and capabilities by building on top of relevant RISC-V standards,
such as the Server SoC, Boot and Runtime Services and Platform Security
specifications for server software executing on the application processor harts
at privilege levels below M. It enables OS and hypervisor vendors to support such
platforms with a single binary OS image distribution model. The requirements posed by this
specification represent a standard set of infrastructural capabilities,
encompassing areas where divergence is typically unnecessary and where novelty
is absent across implementations.
such as the RISC-V Architecture Profiles, Server SoC, Boot and Runtime Services
and Platform Security specifications for server software executing on the application
processor harts at privilege levels below M. It enables OS and hypervisor vendors to
support such platforms with a single binary OS image distribution model. The
requirements posed by this specification represent a standard set of infrastructural
capabilities, encompassing areas where divergence is typically unnecessary and
where novelty is absent across implementations.

To be compliant with this specification, the server platform MUST support all
mandatory requirements and MUST support the listed versions of the specifications.
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83 changes: 81 additions & 2 deletions server_platform_requirements.adoc
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== Server Platform Hardware Requirements

=== RISC-V SoC
=== RISC-V Harts

A RISC-V server platform includes a RISC-V application processor and may include
one or more service processors. These service processors may provide services such
as security and power management to software executing on the application
processors, and they may themselves implement the RISC-V ISA. The requirements
in this section apply solely to harts in the application processors of the SoC.

[width=100%]
[%header, cols="5,25"]
|===
| ID# ^| Requirement
| RVA_010 | The RISC-V application processor harts in the SoC MUST support the
RVA23 ISA profile cite:[RVA23].
2+| _The next major release of the profiles is expected to be RVA24, which is
still under construction. This specification should be updated to comply
with the RVA24 profiles as the profile definition becomes more finalized._

| RVA_020 a| The RISC-V application processor harts in the SoC MUST support the
following extensions:

* Sv48
* Sv48x4
* Svadu
* Sdtrig
* Sdext
* H
* Sscofpmf
* Zkr
* Ssecorrupt
* Ssccfg
* Ssctr
* Sscrind

2+| _Ssccfg, Sscind, and Ssctr are under construction._ +
+
_Many of these mandated extensions are optional in the RVA23 ISA profile.
This requirement is placed here as a placeholder. These mandates may be
moved into a new ISA profile specification._

| RVA_030 | The ISA extensions and associated CSR field widths implemented by
any of the RISC-V application processor harts in the SoC MUST be
identical.
2+| _The RVA23 profile supports a set of optional extensions. The set of
optional extensions implemented by the harts must be identical. Where the
extension supports optionality in the form of field widths (e.g.,
ASIDLEN, VLEN, allowed vstart values, physical address width, debug
triggers, cache-block size, etc.), the implementation of these must also be
identical. Having an identical ISA on all harts allows system software to
migrate tasks among the harts without constraints._

| RVA_040 | The RISC-V application processor harts in the SoC MAY support
different power and performance characteristics but MUST be
otherwise indistinguishable from each other from a software
execution viewpoint.
2+| _All harts in the SoC being indistinguishable from a software execution
viewpoint allows system software to migrate tasks among the harts without
constraints._

| RVA_050 a| The RISC-V application processor hart MUST support:

* Single stepping using the step bit in `dcsr`
* Debug scratch register 0 (`dscratch0`)

| RVA_060 a| The RISC-V application processor hart MUST support:

* At least 4 instruction address match triggers.
* At least 4 load/store address match triggers.
* At least one icount trigger to support single stepping.
* At least one interrupt trigger.
* At least one exception trigger.
* Trigger filtering using `hcontext`.
* Trigger filtering using all VMID encodings supported by the hart.
* Trigger filtering using `scontext`.
* Trigger filtering using all ASID encodings supported by the hart.

| RVA_070 | The RISC-V application processor MUST support at least 6 hardware
performance counters defined by the Zihpm extension in addition to
the three counters defined by Zicntr extension.
|===

A RISC-V server platform is based on a RISC-V SoC with RISC-V application processors.
=== RISC-V SoC

[width=100%]
[%header, cols="5,25"]
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61 changes: 61 additions & 0 deletions server_platform_tests.adoc
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Expand Up @@ -2,6 +2,67 @@

=== Server Platform Hardware Requirements

==== RISC-V Harts

[width=100%]
[%header, cols="8,25"]
|===
| ID# ^| Algorithm
| ME_RVA_010_010 a| For each application processor hart:

. Determine the ISA node in ACPI RHCT table for that hart.
. Parse the ISA string in the ISA node and verify that all
mandatory extensions are supported.
. Verify that the ISA string matches that of hart 0.
. Report the ISA string of hart 0 into the test output log.
| ME_RVA_020_010 | See T_RVA_010_010.
| ME_RVA_030_010 a| . The T_RVA_010_010 verifies that all ISA strings are
identical.
. For each ISA extension reported in the ISA string, if
there are CSRs associated with that extension, then probe
the CSR to determine the width of the CSR fields and the
legal encodings on each application processor hart. The
CSR field widths and legal encodings supported by each
hart must match that of hart 0.
| ME_RVA_040_010 | See ME_RVA_030_010.
| ME_RVA_050_010 a| No test.
| MF_RVA_060_010 a| Install 4 instruction address match triggers using the debug
triggers SBI and verify that each trigger fires.
| MF_RVA_060_020 a| Install 4 load address match triggers using the debug
triggers SBI and verify that each trigger fires.
| MF_RVA_060_030 a| Install 4 store address match triggers using the debug
triggers SBI and verify that each trigger fires.
| MF_RVA_060_040 a| Install an `icount` trigger using the debug triggers SBI and
verify single-step.
| MF_RVA_060_050 a| . Install an interrupt trigger to match supervisor timer
interrupt using the debug triggers SBI.
. Program a timer deadline in `stimecmp`
. Verify that the trigger fires on reaching the programmed
deadline.
| MF_RVA_060_060 a| . Install an exception trigger to match ECALL to S-mode
exception using the debug triggers SBI.
. Transition to U-mode and invoke an ECALL.
. Verify that the trigger fires.
| MF_RVA_060_070 a| . Verify `hcontext` exists.
. Repeat MF_RVA_060_010 and MF_RVA_060_050 with a matching
and non-matching `hcontext` value.
| ME_RVA_060_080 a| . Install and read-back triggers with VMID values between 0
and `VMIDLEN`.
| MF_RVA_060_090 a| . Verify `scontext` exists.
. Repeat MF_RVA_060_010 and MF_RVA_060_050 with a matching
and non-matching `scontext` value.
| ME_RVA_060_100 a| . Install and read-back triggers with ASID values between 0
and `ASIDLEN`.
| ME_RVA_070_010 a| . Request delegation of all HPM counters using the SBI.
. Verify at least 6 programmable HPM counter are implemented.
. Verify that the `scountovf` CSR is implemented
. Verify `cycles` and `instret` are writeable.
. Verify ability to toggle counter enable for each
implemented HPM, `cycles`, and `instret` counters.
|===

<<<

==== RISC-V SoC

[width=100%]
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