Merge pull request #171 from riscv-non-isa/updates-2.0.4-Issues-169

Clarify which addresses are stored in the JTC - Issue 169

branchTrace.adoc

@@ -331,12 +331,12 @@ cache with identical behavior will need to be implemented in the decoder
 software. Even a small cache can provide significant improvement.
 
 The cache shall comprise 2^_cache_size_p_^ entries, each of which can
-contain an instruction address. It will be direct mapped, with each
+contain an instruction address.  The addresses stored in the cache are 
+the targets of uninferable jumps.  It will be direct mapped, with each
 entry indexed by bits _cache_size_p_:1 of the instruction address (or
 __cache_size_p__+1:2 if compressed instructions aren't supported).
 
-Each uninferable jump target is first compared with the entry at its
-index in the cache. If it is found in the cache, the index number is
+Each uninferable jump target is first compared with the entry in the cache at the index derived from the jump target address. If it is found in the cache, the index number is
 traced rather than the target address. If it is not found in the cache,
 the entry at that index is replaced with the current instruction
 address.