1.0.0_rc32. Only reset values remains not DONE.

docs/RISC-V-Trace-Control-Interface.adoc

@@ -1,8 +1,8 @@
 [[header]]
 :description: RISC-V Trace Control Interface
 :company: RISC-V.org
-:revdate:  May 07, 2024
-:revnumber: 1.0.0_rc31
+:revdate:  May 21, 2024
+:revnumber: 1.0.0_rc32
 :revremark: Stable state (ready for Freeze)
 :url-riscv: http://riscv.org
 :doctype: book
@@ -52,9 +52,10 @@ Change is extremely unlikely.
 
 PDF generated on: {localdatetime}
 
-=== Version 1.0.0_rc31
-* 2024-05-07
-** Ready for Freeze.
+=== Version 1.0.0_rc32
+* 2024-05-21
+** All notes from ARC (except reset values) DONE.
+** Only reset values remaining to be changed.
 
 [Preface]
 == Copyright and license information
@@ -551,7 +552,7 @@ Instruction trace generation mode +
 |10 |--|Reserved|--|0
 |11  |trTeInstTrigEnable |*1:* Allows `trTeInstTracing` to be set or cleared by Trace-on
 and Trace-off signals generated by the corresponding trigger module.|WARL|0
-|12  |trTeInstStallOrOverflow |Set to 1 by hardware when trace buffer overflow (also know as trace lost) occurs, or when the TE requests a hart stall. Clears to 0 at TE reset or when the trace is enabled (`trTeEnable` set to 1). Write 1 to clear.|RW1C|0
+|12  |trTeInstStallOrOverflow |Set to 1 by hardware when trace buffer overflow (also known as trace lost) occurs, or when the TE requests a hart stall. Clears to 0 at TE reset or when the trace is enabled (`trTeEnable` set to 1). Write 1 to clear.|RW1C|0
 |13 |trTeInstStallEna |
 *0:* If TE cannot send a message, the message is dropped. The protocol dependent overflow instruction trace synchronization message/packet is generated when the trace is restarted, so the decoder will know that trace is lost and must reset any internal decoder state. +
 *1:* If TE cannot send a message, the hart is stalled until it can. With this option execution of instructions by the hart may be intrusively affected, but in many cases it is acceptable.
@@ -585,6 +586,8 @@ Trace recording/protocol format: +
 |31:27 |--|Reserved|--|0
 |===
 
+NOTE: Writing to this register while trace is enabled may unintentionally change a value of `trTeInstTracing` bit because that bit may dynamically change by triggers.
+
 .*Register: trTeImpl: Trace Encoder Implementation Register (trBaseEncoder+0x004)*
 [cols="7%,30%,~,8%,8%",options="header",]
 |===
@@ -645,7 +648,7 @@ Determine which filters defined in <<Trace Encoder Filter Registers, Trace Encod
 |0 |trTeDataImplemented|Read as 1 if data trace is implemented.|RO|SD
 |1 |trTeDataTracing |*1:* Data trace is being generated. Written from a trace tool or controlled by triggers. When `trTeDataTracing`=1, data trace  may be subject to additional filtering in some implementations.|WARL|SD
 |2 |trTeDataTrigEnable|Global enable/disable for data trace triggers|WARL|0
-|3 |trTeDataStallOrOverflow |Written to 1 by hardware when an overflow message is generated or when the TE requests a hart stall due to data trace. Clears to 0 at TE reset or when the trace is enabled (`trTeEnable` set to 1). Write 1 to clear. |RW1C|0
+|3 |trTeDataStallOrOverflow |Set to 1 by hardware when data trace causes trace buffer overflow, or when the TE requests a hart stall due to data trace. Clears to 0 at TE reset or when the trace is enabled (`trTeEnable` set to 1). Write 1 to clear. |RW1C|0
 |4 |trTeDataStallEna |
 *0:* If TE cannot send data trace messages, an overflow message is generated when the trace is restarted. +
 *1:* If TE cannot send data trace messages, the hart is stalled until it can.
@@ -659,11 +662,13 @@ Determine which filters defined in <<Trace Encoder Filter Registers, Trace Encod
 *0:* Only send full (unmodified) addresses +
 *1:* Use XOR compression +
 *2:* Use differential compression +
-*3:* Dynamically select XOR or differential on a per-packet basis in order to minimize packet length
+*3:* Protocol defined address compression
 |WARL|SD
 |31:20 |--|Reserved|--|0
 |===
 
+NOTE: Writing to this register while trace is enabled may unintentionally change a value of `trTeDataTracing` bit because that bit may dynamically change by triggers.
+
 NOTE: Applicability of different `trTeData??` fields for each trace encoding protocol is described in a document which defines the protocol (and not all fields are applicable to all protocols).
 
 .*Register: trTeDataFilters: Trace Data Filters Register (trBaseEncoder+0x01C)*
@@ -721,7 +726,7 @@ Mode used by Timestamp unit: +
 |WARL|SD
 |7 |--|Reserved|--|0
 |9:8 |trTsPrescale |*Internal System or Core* timestamp only. +
-Prescale timestamp clock by 2^(2*trTsPrescale) (1, 4, 16, 64).
+Prescale timestamp input clock by 2^(2*trTsPrescale). It will be divided by 1, 4, 16, 64 respectively.
 |WARL|0
 |14:10 |--|Reserved|--|0
 |15 |trTsEnable |Enable for timestamp field in trace messages/packets (for Trace Encoder only). |WARL|0
@@ -1205,7 +1210,7 @@ Table below shows typical Trace RAM Sink configurations. Implementing other conf
 [cols="10%,15%,30%,15%,15%,15%",options="header",]
 |===
 |*Mode*      |*trRamStart* |*trRamLimit* |*trRamWP* |*trRamRP* |*trRamData*
-|SRAM        |0 |Hard coded to max size (2^M) at reset, but can be possibly trimmed|Required  |Required |Required
+|SRAM        |0 |Hard coded to max size (2^M - A) at reset, but can be possibly trimmed|Required  |Required |Required
 |SMEM Generic |Any (2^N aligned) |Any (`trRamStart` + 2^M - A) - must be set by trace tool |Required  |Not implemented|Not implemented
 |SMEM Fixed   |Fixed (2^N aligned) |Fixed to max size at reset (`trRamStart` + 2^M - A), but can be possibly trimmed |Required  |Not implemented|Not implemented
 |===
@@ -1560,11 +1565,11 @@ Reset and Discovery should be performed as follows:
 
 * Reset the component by setting `tr??Active` = 0.
 * Read-back and wait until `tr??Active` = 0 is read.
-* Optionally save `tr??Control` register as it holds all reset values of all fields. It may be cached/shadowed and trace tool may execute faster write-only (intead a read-modify-write) operations.
 * Release from reset by setting `tr??Active` = 1 and wait for `tr??Active` = 1 to be read (to confirm component is not in reset). 
 
-IMPORTANT: When performing a write which is setting `tr??Active` = 1, no other bits should be changed. 
+IMPORTANT: When performing a write which is setting `tr??Active` = 1, no other bits should be changed (read-modify write is recommended)
 
+* Optionally save `tr??Control` register as it holds all reset values of all fields. It may be cached/shadowed and trace tool may execute faster write-only (intead a read-modify-write) operations.
 * Handle `tr??VerMinor/Major` as described in 'Versioning of Components' chapter.
 ** If `tr??VerMajor` is 0 (for Trace Encoder component) either handle it as pre-ratified/initial version 0 or generate fatal error with an appropriate error message.
 * Read `tr??Impl` and compare `tr??ComType` field with expected value.