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Merge pull request #106 from riscv-software-src/dev
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bump to 0.12.0
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neelgala authored Feb 22, 2024
2 parents 95bec38 + e24cb24 commit 41d184b
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25 changes: 25 additions & 0 deletions .github/pull_request_template.md
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@@ -0,0 +1,25 @@
<FOR DOC UPDATES FILL ONLY DESCRIPTION AND RELATED ISSUES SECTION AND REMOVE THE OTHERS>

#DEVELOPMENT PRs SHOULD BE TO DEV BRANCH ONLY

## Description

> Provide a detailed description of the changes performed by the PR.
### Related Issues

> Please list all the issues related to this PR. Use NA if no issues exist.
### Update to/for Ratified/Unratified Extensions or to framework

- [ ] Ratified
- [ ] Unratified
- [ ] Framework

### List Extensions

> List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR.
### Mandatory Checklist:

- [ ] Make sure to have created a suitable entry in the CHANGELOG.md under `[WIP-DEV]` section.
1 change: 0 additions & 1 deletion .github/workflows/main.yml
Original file line number Diff line number Diff line change
Expand Up @@ -95,4 +95,3 @@ jobs:
# asset_content_type: application/pdf



95 changes: 65 additions & 30 deletions .github/workflows/test.yml
Original file line number Diff line number Diff line change
@@ -1,26 +1,19 @@
# This is a basic workflow to help you get started with Actions

name: test

# Controls when the action will run.
on:
# Triggers the workflow on push or pull request events but only for the master branch
pull_request:
branches: [ master ]

# Allows you to run this workflow manually from the Actions tab
branches:
-master
-dev
workflow_dispatch:

# A workflow run is made up of one or more jobs that can run sequentially or in parallel
jobs:
# This workflow contains a single job called "build"
build:
# The type of runner that the job will run on
runs-on: ubuntu-latest

# Steps represent a sequence of tasks that will be executed as part of the job
strategy:
matrix:
cgf_files: ["./sample_cgfs/*.cgf"]
architecture: ["rv32e", "rv32i", "rv64i", "rv32i_64i"]
steps:
# Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it
- uses: actions/checkout@v2
- name: Set up Python
uses: actions/setup-python@v2
Expand All @@ -33,10 +26,63 @@ jobs:
pip install -r riscv_ctg/requirements.txt
pip install --editable .
- name: Run rv32i
run: riscv_ctg -r -d rv32i -bi rv32i -cf sample_cgfs/dataset.cgf -cf sample_cgfs/rv32i.cgf -v debug -p $(nproc)
- name: Run RISC-V CTG for RV32E
run: |
set -e
for cgf_file in ./sample_cgfs/*.cgf; do
if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then
if [[ "$cgf_file" == *rv32e* ]] && [ "${{matrix.architecture}}" == "rv32e" ] ; then
cmd="riscv_ctg -r -d ./tests -bi rv32e -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)"
echo $cmd
eval $cmd || { echo "Error executing command: $cmd"; exit 1; }
fi
fi
done
- name: Run RISC-V CTG for RV32I
run: |
set -e
for cgf_file in ./sample_cgfs/*.cgf; do
if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then
if [[ "$cgf_file" != *rv32e* ]] && [[ "cgf_file" == *rv32* ]] && [ "${{matrix.architecture}}" == "rv32i" ] ; then
cmd="riscv_ctg -r -d ./tests -bi rv32i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)"
echo $cmd
eval $cmd || { echo "Error executing command: $cmd"; exit 1; }
fi
fi
done
- name: Run RISC-V CTG for RV64I
run: |
set -e
for cgf_file in ./sample_cgfs/*.cgf; do
if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then
if [[ "$cgf_file" == *rv64* ]] && [ "${{matrix.architecture}}" == "rv64i" ] ; then
cmd="riscv_ctg -r -d ./tests -bi rv64i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)"
echo $cmd
eval $cmd || { echo "Error executing command: $cmd"; exit 1; }
fi
fi
done
- name: Run RISC-V CTG for RV64I and RV32I
run: |
set -e
for cgf_file in ./sample_cgfs/*.cgf; do
if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then
if [[ "$cgf_file" != *rv32e* ]] && [[ "$cgf_file" != *rv32* ]] && [[ "$cgf_file" != *rv64* ]] && [ "${{matrix.architecture}}" == "rv32i_64i" ] ; then
for arch in rv32i rv64i; do
cmd="riscv_ctg -r -d ./tests -bi $arch -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)"
echo $cmd
eval $cmd || { echo "Error executing command: $cmd"; exit 1; }
done
fi
fi
done
check-version:
if: github.ref == 'refs/heads/master'
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
Expand All @@ -51,21 +97,8 @@ jobs:
echo "Versions are equal in Changelog and init.py."
else
echo "Versions are not equal in Changelog and init.py."
exit 1
exit 1
fi
check-version-changelog:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2

- uses: actions-ecosystem/action-get-latest-tag@v1
id: get-latest-tag

- name: version check
run: |
export CHNGVER=$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md);
echo "CHANGELOG VERSION: $CHNGVER"
export TAGVER=${{ steps.get-latest-tag.outputs.tag }};
echo "TAG VERSION: $TAGVER"
if [ "$CHNGVER" = "$TAGVER" ]; then
Expand All @@ -74,3 +107,5 @@ jobs:
else
echo "Changelog updated."
fi
43 changes: 43 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,49 @@

This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).

Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch.
Only when a release to the main branch is done, the contents of the WIP-DEV are put under a
versioned header while the `WIP-DEV` is left empty

## [0.12.0] - 2024-02-22
- Update generator.py to take care of hard coded register testcases only if a hard coded register is assigned in the op_comb node of a coverpoint of an instruction.
- Add hardcoded register testcases to dataset.cgf and rv32im.cgf
- Define rs1_val_data for c.ldsp in imc.yaml
- Update "opcode" to "mnemonics" in the cgf files
- Delete main.yml
- Update test.yml for CI
- Define rs1_val_data for instructions from zicfiss.cgf in template.yaml
- Add "warning" in the verbose definition
- Add unratified Zicfiss extension
- Add unratified Zicfilp extension
- Add corner case of division for division operations for RV64
- Fix csr_comb to write test information
- Add unratified Zaamo subcomponent of A extension
- Add unratified B extension
- Fix issues with csr_comb
- Minor fix in kslraw.u in rv32ip
- Fix incorrect 'sig:' entry in aes32dsi in template.yaml
- Add sig and sz for instructions in template.yaml
- Minor change of rd definition in c.lui in rv32ec
- Minor fix in rv32i_k
- Add rs1_val_data, rs2_val_data, imm_val_data for instructions in template.yaml
- Comment xlenlim out of val_comb in rv32i_b, rv64i_b
- Fix the formats of leading_ones, leading_zeros, trailing_ones, trailing_zeros for instructions in rv32i_b, rv32e_b
- Add op_comb for instructions in rv32i_zcb
- Add rs1_val_data for instructions in imc.yaml
- Add op_comb and val_comb for instructions in rv32ic, rv64ic, rv32ec
- Add corner case of division for division operations for RV32
- Comment print statements out from generator.py
- Fix whitespaces on empty lines in yaml template files.
- Add unratified Zabha extension
- Add support for unratified Zcmop extension
- Add support for unratified Zimop extension
- Add missing coverage for hard coded register testcases
- Updated CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release cadence.
- Add Zifencei, Bit Manipulation and Privilege tests cgf files for RV32E
- Add unratified Zacas extension
- Add support for standard Atomic(A) extension

## [0.11.1] - 2023-08-15
- Fixed hex values handling for K extensions
- Fixed set indexing error during opcomb gen
Expand Down
71 changes: 50 additions & 21 deletions CONTRIBUTING.rst
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Expand Up @@ -2,9 +2,9 @@
.. highlight:: shell

============
Contributing
============
======================
Developer Contribution
======================

Contributions are welcome, and they are greatly appreciated and credit will always be given.

Expand All @@ -30,15 +30,31 @@ If you are proposing a feature:
* Remember that this is a volunteer-driven project, and that contributions
are welcome :)

Git Strategy
------------

The repo adopts a simple git strategy where all contributions to the repo are made to the ``dev``
branch (i.e. all Pull-Requests must use ``dev`` as the target branch). On a monthly cadence (decided
and controlled by the SIG-ARCH-TEST members) the ``dev`` branch will be merged to the ``main`` to by
the official maintainers of the repo. This will create an official release capturing all the
development over the month into a single release.

To implement the above strategy successfully the following needs be followed:

* Developers: All pull-requests from developers must target the ``dev`` branch and the PR must
contain an entry in the CHANGELOG.md file under `[WIP-DEV]` section.
* Maintainers: When a making a release the maintainers shall assign semantic version number by
updating the CHANGELOG and the respective python files before raising a PR from the `dev` to `main`.

Get Started!
------------

Ready to contribute? Here's how to set up `riscv_ctg` for local development.

1. Fork the `riscv_ctg` repo on GitHub.
2. Clone your fork locally::
2. Clone your fork locally and checkout the ``dev`` branch::

$ git clone https://github.com/riscv-software-src/riscv-ctg.git
$ git clone https://github.com/riscv-software-src/riscv-ctg.git -b dev

3. Create an issue and WIP merge request that creates a working branch for you::

Expand All @@ -58,33 +74,46 @@ Ready to contribute? Here's how to set up `riscv_ctg` for local development.
$ git commit -m "Your detailed description of your changes."
$ git push origin name-of-your-bugfix-or-feature

6. Submit a merge request through the GitHub website.
6. Submit a pull-request through the GitHub website. Make sure the pull-request is on the `dev`
branch of the origin repo.

7. Do not forget to make an entry in the CHANGELOG.md file under the `[WIP-DEV]` section
highlighting the changes you have done.

Merge Request Guidelines
----------------------------
------------------------

Before you submit a merge request, check that it meets these guidelines:

1. The merge request should include tests.
1. The merge request should include tests (if any).
2. If the merge request adds functionality, the docs should be updated.
3. The merge request should work for Python 3.6, 3.7 and 3.8, and for PyPy.
and make sure that the tests pass for all supported Python versions.
3. The target branch must always be the `dev` branch.


Versioning (only for maintainers)
---------------------------------

When issuing pull requests to the main branch (from dev), a version entry in the CHANGELOG.md is mandatory. The tool adheres to
the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must
be followed while assigning a new version number :

- Patch-updates: all doc updates (like typos, more clarification,etc).
- Minor-updates: Fixing bugs in current features, adding new features which do not break current
features or working. Adding new extensions.
- Major-updates: Backward incompatible changes.

Tips
----
Note: You can have either a patch or minor or major update.
Note: In case of a conflict, the maintainers will decide the final version to be assigned.

To run a subset of tests::
To update the version of the python package for deployment you can use `bumpversion` (installed
using ``pip install bumpversion``)::

$ pytest tests.test_riscv_ctg
$ bumpversion --no-tag --config-file setup.cfg patch # last arg can be: major or minor or patch

If you don't have bumpversion installed you can manually update the version in the following files:

Deploying
---------
- change the value of variable ``current_version`` in `./setup.cfg`
- change the value of variable ``__version__`` in `./riscv_ctg/__init__.py`

A reminder for the maintainers on how to deploy.
Make sure all your changes are committed.
Then run::

$ bumpversion --no-tag --config-file setup.cfg patch # possible: major / minor / patch
$ git push origin name-of-your-branch

2 changes: 1 addition & 1 deletion riscv_ctg/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,4 +4,4 @@

__author__ = """InCore Semiconductors Pvt Ltd"""
__email__ = '[email protected]'
__version__ = '0.11.1'
__version__ = '0.12.0'
5 changes: 3 additions & 2 deletions riscv_ctg/cross_comb.py
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,8 @@
'pphrrformat' : '$instr $rd, $rs1, $rs2',
'ppbrrformat' : '$instr $rd, $rs1, $rs2',
'prrformat' : '$instr ',
'prrrformat' : '$instr'
'prrrformat' : '$instr',
'dcasrformat' : '$instr '
}
'''Dictionary to store instruction formats'''

Expand Down Expand Up @@ -497,4 +498,4 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, full_solution):
label = cov_label,
extension = extension
)
)
)
11 changes: 6 additions & 5 deletions riscv_ctg/csr_comb.py
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
'or' : -3,
}

CSR_REGS = ['mvendorid', 'marchid', 'mimpid', 'mhartid', 'mstatus', 'misa', 'medeleg', 'mideleg', 'mie', 'mtvec', 'mcounteren', 'mscratch', 'mepc', 'mcause', 'mtval', 'mip', 'pmpcfg0', 'pmpcfg1', 'pmpcfg2', 'pmpcfg3', 'mcycle', 'minstret', 'mcycleh', 'minstreth', 'mcountinhibit', 'tselect', 'tdata1', 'tdata2', 'tdata3', 'dcsr', 'dpc', 'dscratch0', 'dscratch1', 'sstatus', 'sedeleg', 'sideleg', 'sie', 'stvec', 'scounteren', 'sscratch', 'sepc', 'scause', 'stval', 'sip', 'satp', 'vxsat', 'fflags', 'frm', 'fcsr']
CSR_REGS = ['mvendorid', 'marchid', 'mimpid', 'mhartid', 'mstatus', 'misa', 'medeleg', 'mideleg', 'mie', 'mtvec', 'mcounteren', 'mscratch', 'mepc', 'mcause', 'mtval', 'mip', 'pmpcfg0', 'pmpcfg1', 'pmpcfg2', 'pmpcfg3', 'mcycle', 'minstret', 'mcycleh', 'minstreth', 'mcountinhibit', 'tselect', 'tdata1', 'tdata2', 'tdata3', 'dcsr', 'dpc', 'dscratch0', 'dscratch1', 'sstatus', 'sedeleg', 'sideleg', 'sie', 'stvec', 'scounteren', 'sscratch', 'sepc', 'scause', 'stval', 'sip', 'satp', 'vxsat', 'fflags', 'frm', 'fcsr', 'CSR_SRMCFG']
csr_regs_capture_group = f'({"|".join(CSR_REGS)})'
csr_regs_with_modifiers_capture_group = r'(write|old) *\( *"' + csr_regs_capture_group + r'" *\)'

Expand Down Expand Up @@ -260,7 +260,7 @@ class GeneratorCSRComb():
'''

def __init__(self, base_isa, xlen, randomize):
self.base_isa = base_isa
self.base_isa = base_isa + "_Zicsr"
self.xlen = xlen
self.randomize = randomize

Expand Down Expand Up @@ -366,7 +366,7 @@ def csr_comb(self, cgf_node):
instr_dict_csr_read_and_sig_upds.append({
'csr_reg': csr_reg, 'dest_reg': dest_reg, 'offset': offset
})
offset += 4
offset += (self.xlen >> 3)

instr_dict.append((instr_dict_csr_writes, instr_dict_csr_read_and_sig_upds, instr_dict_csr_restores))

Expand Down Expand Up @@ -413,8 +413,9 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, instr_dict):

case_str = ''.join([case_template.safe_substitute(xlen = self.xlen, num = i, cov_label = cov_label) for i, cond in enumerate(cgf_node.get('config', []))])
test_str = part_template.safe_substitute(case_str = case_str, code = '\n'.join(code))

with open(fprefix + '_csr-comb.S', 'w') as fp:
fname = fprefix + '_csr-comb.S'
logger.debug("Writing Test to %s", str(fname))
with open(fname, 'w') as fp:
fp.write(usage_str + csr_comb_test_template.safe_substitute(
isa = self.base_isa.upper(), # how to get the extensions?
test = test_str,
Expand Down
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